Hyundai Micro Electronics
GMS81C2020/GMS81C2120
The interrupts are controlled by the interrupt master enable
flag I-flag (bit 2 of PSW), the interrupt enable register
(IENH, IENL) and the interrupt request flags (in IRQH,
IRQL) except Power-on reset and software BRK interrupt.
Reset/Interrupt
Symbol Priority Vector Addr.
Hardware Reset
External Interrupt 0 INT0
External Interrupt 1 INT1
Timer 0
Timer 1
RESET
-
1
2
3
4
-
FFFEH
FFFAH
FFF8H
FFF6H
FFF4H
FFF2H
FFF0H
FFEEH
FFECH
FFEAH
FFE8H
FFE6H
Interrupt enable registers are shown in Figure 19-2 . These
registers are composed of interrupt enable flags of each in-
terrupt source, these flags determines whether an interrupt
will be accepted or not. When enable flag is "0", a corre-
sponding interrupt source is prohibited. Note that PSW
contains also a master enable bit, I-flag, which disables all
interrupts at once.
Timer 0
Timer 1
-
-
-
-
-
-
-
-
-
-
-
A/D Converter
Watch Dog Timer
Basic Interval Timer BIT
Serial Interface SPI
A/D C
WDT
5
6
7
8
Table 19-1 Interrupt Priority
Interrupt Enable Register High
ADDRESS : E2H
RESET VALUE : 0000----
INT0E
INT1E
T0E
T1E
-
-
-
-
-
-
-
IENH
IENL
Interrupt Enable Register Low
ADE WDTE BITE
ADDRESS : E3H
RESET VALUE : 0000----
SPIE
-
Enables or disables the interrupt individually
If flag is cleared, the interrupt is disabled.
0 : Disable
1 : Enable
Interrupt Request Register High
INT0IF INT1IF T0IF
ADDRESS : E4H
RESET VALUE : 0000----
T1IF
-
-
-
-
-
-
-
IRQH
IRQL
Interrupt Request Register Low
ADIF WDTIF BITIF
ADDRESS : E5H
RESET VALUE : 0000----
SPIIF
-
Shows the interrupt occurrence
0 : Not occurred
1 : Interrupt request is occurred
Figure 19-2 Interrupt Enable Registers and Interrupt Request Registers
When an interrupt is occured, the I-flag is cleared and dis-
able any further interrupt, the return address and PSW are
pushed into the stack and the PC is vectored to. Once in the
interrupt service routine the source(s) of the interrupt can
be determined by polling the interrupt request flag bits.
The interrupt request flag bit(s) must be cleared by soft-
ware before re-enabling interrupts to avoid recursive inter-
rupts. The Interrupt Request flags are able to be read and
written.
Nov. 1999 Ver 0.0
preliminary
67
HYNIX [ HYNIX SEMICONDUCTOR ]
