GMS81C2020/GMS81C2120
Hyundai Micro Electronics
20. WATCHDOG TIMER
The purpose of the watchdog timer is to detect the mal-
function (runaway) of program due to external noise or
other causes and return the operation to the normal condi-
tion.
The 7-bit binary counter is cleared by setting WDTCL(bit7
of WDTR) and the WDTCL is cleared automatically after
1 maching cycle.
The RC oscillated watchdog timer is activated by setting
the bit RCWDT as shown below.
The watchdog timer has two types of clock source.
:
The first type is an on-chip RC oscillator which does not
require any external components. This RC oscillator is sep-
arate from the external oscillator of the Xin pin. It means
that the watchdog timer will run, even if the clock on the
Xin pin of the device has been stopped, for example, by en-
tering the STOP mode.
LDM
LDM
STOP
NOP
NOP
:
CKCTLR,#3FH; enable the RC-osc WDT
WDTR,#0FFH; set the WDT period
; enter the STOP mode
; RC-osc WDT running
The RCWDT oscillation period is vary with temperature,
VDD and process variations from part to part (approxi-
mately, 40~120uS ). The following equation shows the
RCWDT oscillated watchdog timer time-out.
The other type is a prescaled system clock.
The watchdog timer consists of 7-bit binary counter and
the watchdog timer data register. When the value of 7-bit
binary counter is equal to the lower 7 bits of WDTR, the
interrupt request flag is generated. This can be used as
WDT interrupt or reset the CPU in accordance with the bit
WDTON .
TR C W D T = C LK R C W D T ×28×[W D TR.6~0]+ (C LK R C W D T ×28)/2
w here, C LK R C W D T = 40~120uS
In addition, this watchdog timer can be used as a simple 7-
bit timer by interrupt WDTIF. The interval of watchdog
timer interrupt is decided by Basic Interval Timer. Interval
equation is as below.
Note: Because the watchdog timer counter is enabled af-
ter clearing Basic Interval Timer, after the bit WD-
TON set to "1", maximum error of timer is depend on
prescaler ratio of Basic Interval Timer.
TWDT = [WDTR.6~0] × Interval of BIT
Clock Control Register
ADDRESS : ECH
RESET VALUE : -0010111
Bit Manipulation Not Available
-
WAKEUP RCWDT WDTON
BTCL
X
BTS2
X
BTS1
X
BTS0
X
CKCTLR
-
0
X
1
Watchdog Timer Register
ADDRESS : EDH
RESET VALUE : 01111111
WDTCL
7-bit Watchdog Counter Register
WDTR
Bit Manipulation Not Available
WAKEUP
STOP
RCWDT
WDTR (7-bit)
WDTCL
8
÷
BTCL
Clear
WDTCL WDTON
RESET
16
÷
32
÷
÷
÷
÷
÷
÷
64
1
0
0
1
fXI
MUX
To RESET
128
256
7-bit Counter
OFD
BITR (8-BIT)
512
Overflow Detection
BTS[2:0]
1024
Watchdog Timer
Interrupt Request
Basic Interval Timer
Interrupt
BITIF
Internal RC OSC
Figure 20-1 Block Diagram of Watchdog Timer
72
preliminary
Nov. 1999 Ver 0.0
HYNIX [ HYNIX SEMICONDUCTOR ]
