GMS81C2020/GMS81C2120
Hyundai Micro Electronics
19. INTERRUPTS
The GMS81C2020 and GMS81C2120 interrupt circuits
consist of Interrupt enable register (IENH, IENL), Inter-
rupt request flags of IRQH, IRQL, Interrupt Edge Selec-
tion Register (IEDS), priority circuit and Master enable
flag("I" flag of PSW). The configuration of interrupt cir-
cuit is shown in Figure and Interrupt priority is shown in
Table 19-1 .
only if the interrupt was transition-activated.
The Timer 0 and Timer 1 Interrupts are generated by T0IF
and T1IF, which are set by a match in their respective tim-
er/counter register. The AD converter Interrupt is generat-
ed by ADIF which is set by finishing the analog to digital
conversion. The Watch dog timer Interrupt is generated by
WDTIF which set by a match in Watch dog timer register
(when the bit WDTON is set to "0"). The Basic Interval
Timer Interrupt is generated by BITIF which is set by a
overflowing of the Basic Interval Timer Register(BITR).
The Serial Peripheral Interface (SPI) is generated by SPIIF
which is set by communicating with other peripheral of mi-
crocontroller devices (by finishing the data transmission).
The External Interrupts INT0 and INT1 can each be transi-
tion-activated (1-to-0, 0-to-1 and both transiton).
The flags that actually generate these interrupts are bit
INT0IF and INT1IF in Register IRQH. When an external
interrupt is generated, the flag that generated it is cleared
by the hardware when the service routine is vectored to
Internal bus line
IENH[7:4]
I-flag is in PSW, it is cleared by "DI", set by
"EI" instruction.When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by "RETI" instruction, I-flag is set to
Interrupt Enable
Register (Higher byte)
IRQH
IEDS[3:0]
"1" by hardware.
7
INT0IF
INT1IF
T0IF
External Int. 0
External Int. 1
Release STOP
6
5
4
Timer 0
Timer 1
To CPU
T1IF
I Flag
IRQH[7:4]
Interrupt Master
Enable Flag[PSW.2]
Priority
Control
IRQL[7:4]
7
6
ADIF
A/D Converter
WDT
WDTIF
BITIF
Interrupt
Vector
Address
Generator
5
4
BIT
SPI
SPIIF
Interrupt Enable
Register (Lower byte)
IRQL
IENL[7:4]
Internal bus line
Figure 19-1 Block Diagram of Interrupt Function
66
preliminary
Nov. 1999 Ver 0.0
HYNIX [ HYNIX SEMICONDUCTOR ]
