GMS81C1102 / GMS81C1202
A/D Control Register
ADDRESS : EAH
RESET VALUE : --000001
-
-
ADCM
ADEN
ADS2
ADS1
ADS0
ADST
ADSF
Reserved
A/D Status bit
0 : A/D Conversion is in process
1 : A/D Conversion is completed
Analog Channel Select
000 : Channel 0 ( RB0/AN0 )
001 : Channel 1 ( RA1/AN1 )
010 : Channel 2 ( RA2/AN2 )
011 : Channel 3 ( RA3/AN3)
100 : Channel 4 ( RA4/AN4 )
101 : Channel 5 ( RA5/AN5 )
110 : Channel 6 ( RA6/AN6 )
111 : Channel 7 ( RA7/AN7 )
A/D Start bit
1 : A/D Conversion is started
After 1 cycle, cleared to "0"
0 : Bit force to zero
A/D Enable bit
1 : A/D Conversion is enable
0 : A/D Converter module shut off
and consumes no operation current
A/D Result Data Register
ADCR7 ADCR6 ADCR5
ADDRESS : EBH
RESET VALUE : Undefined
ADCR4
ADCR3
ADCR2
ADCR1
ADCR0
ADCR
Figure 18-2 A/D Converter Registers
A/D Converter Cautions
(1) Input range of AN0 to AN7
ENABLE A/D CONVERTER
A/D INPUT CHANNEL SELECT
ANALOG REFERENCE SELECT
A/D START ( ADST = 1 )
NOP
The input voltages of AN0 to AN7 should be within the
specification range. In particular, if a voltage above VDD
(or AVref)or below VSS is input (even if within the absolute max-
imum rating range), the conversion value for that channel can not
be indeterminate. The conversion values of the other channels
may also be affected.
(2) Noise countermeasures
In order to maintain 8-bit resolution, attention must be paid to
noise on pins AVref(or VDD)and AN0 to AN7. Since the effect
increases in proportion to the output impedance of the an-
alog input source, it is recommended that a capacitor be con-
nected externally as shown in Figure 18-4 in order to reduce
noise
.
ADSF = 1
YES
Analog
NO
AN0~AN7
Input
100~1000pF
READ ADCR
Figure 18-3 A/D Converter Operation Flow
Figure 18-4 Analog Input Pin Connecting Capacitor
Jan. 2002 ver 2.0
55
HYNIX [ HYNIX SEMICONDUCTOR ]
