GMS81C1102 / GMS81C1202
If it needed more higher frequency of PWM, it should be
reduced resolution.
determined by the bit POL ( 1: Low, 0: High ).
It can be changed duty value when the PWM output. How-
erver the changed duty value is output after the current pe-
riod is over. And it can be maintained the duty value at
present output when changed only period value shown as
Figure 16-12 . As it were, the absolute duty time is not
changed in varying frequency. But the changed period val-
ue must greater than the duty value
Frequency
Resolution
T1CK[1:0]
T1CK[1:0]
T1CK[1:0]
= 10(1uS)
= 00(125nS) = 01(250nS)
10-bit
9-bit
8-bit
7-bit
7.8KHz
15.6KHz
31.2KHz
62.5KHz
3.9KHz
7.8KHz
0.98KHZ
1.95KHz
3.90KHz
7.81KHz
15.6KHz
31.2KHz
Note: At PWM output start command, one first pulse would
be output abnormally. Because if user writes regis-
ter values while timer is in operaiton, these register
could be set with certain values at first. To prevent
this operation, user must stop PWM timer clock and
then set the duty and the period register values.
Table 16-2 PWM Frequency vs. Resolution at 8MHz
The bit POL of TM1 decides the polarity of duty cycle.
If the duty value is set same to the period value, the PWM
output is determined by the bit POL ( 1: High, 0: Low ).
And if the duty value is set to "00H", the PWM output is
.
ADDRESS : D2H
RESET VALUE : 00000000
T1CK1
X
T1CK0
X
T1CN
X
T1ST
X
POL
16BIT
PWME
CAP1
TM1
X
-
0
-
1
-
0
-
ADDRESS : D5H
RESET VALUE : ----0000
PWM0HR3PWM0HR2PWM0HR1PWM0HR0
PWM0HR
Bit Manipulation Not Available
-
-
-
-
X
X
X
X
Period High
PWM0HR[3:2]
Duty High
X : The value IS "0" or "1" corresponding your operation.
T1ST
T1PPR(8-bit)
COMPARATOR
T0 clock source
0 : Stop
1 : Start
RB4/
PWM0
S
R
Q
CLEAR
1
MUX
T1 ( 8-bit )
PWM0O
[RBFUNC.4]
1
2
8
÷
÷
÷
fxin
POL
COMPARATOR
T1CN
T1CK[1:0]
Slave
T1PDR(8-bit)
PWM0HR[1:0]
Master
T1PDR(8-bit)
Figure 16-10 PWM Mode
Jan. 2002 ver 2.0
51
HYNIX [ HYNIX SEMICONDUCTOR ]
