GMS81C1102 / GMS81C1202
fxin
T1
00 01
02
03
04
05
7F
80
81
3FF 00 01
02
03
PWM
POL=1
PWM
POL=0
Duty Cycle [ 80H x 125nS = 16uS ]
Period Cycle [ 3FFH x 125nS = 127.875uS, 7.8KHz ]
T1CK[1:0] = 00 ( fxin )
PWM0HR = 0CH
T1PPR (8-bit)
Period PWM0HR3PWM0HR2
1
1
FFH
T1PPR = FFH
T1PDR = 80H
T1PDR (8-bit)
80H
PWM0HR1PWM0HR0
Duty
0
0
Figure 16-11 Example of PWM at 8MHz
T1CK[1:0] = 10 ( 1uS )
PW M H R = 00H
T1PPR = 0EH
Write T1PPR to 0AH
Period changed
T1PDR = 05H
Source
clock
T1
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 01 02 03 04 05 06 07 08 09 0A 01 02 03 04 05
PWM
POL=1
Duty Cycle
[ 05H x 1uS = 5uS ]
Duty Cycle
[ 05H x 1uS = 5uS ]
Duty Cycle
[ 05H x 1uS = 5uS ]
Period Cycle [ 0EH x 1uS = 14uS, 71KHz ]
Period Cycle [ 0AH x 1uS = 10uS, 100KHz ]
Figure 16-12 Example of Changing the Period in Absolute Duty Cycle (@8MHz)
52
Jan. 2002 ver 2.0
HYNIX [ HYNIX SEMICONDUCTOR ]
