GMS81C1102 / GMS81C1202
19. INTERRUPTS
The GMS81C1202 interrupt circuits consist of Interrupt
enable register (IENH, IENL), Interrupt request flags of
IRQH, IRQL, Interrupt Edge Selection Register (IEDS),
priority circuit and Master enable flag("I" flag of PSW).
The configuration of interrupt circuit is shown in Figure
19-1 and Interrupt priority is shown in Table 19-1 .
only if the interrupt was transition-activated.
The Timer 0 and Timer 1 Interrupts are generated by T0IF,
T1IF, which are set by a match in their respective timer/
counter register. The AD converter Interrupt is generated
by ADIF which is set by finishing the analog to digital con-
version. The Watch dog timer Interrupt is generated by
WDTIF which set by a match in Watch dog timer register
( when the bit WDTON is set to "0"). The Basic Interval
Timer Interrupt is generated by BITIF which is set by a
overflowing of the Basic Interval Timer Register(BITR).
The External Interrupts INT0 and INT1 can each be transi-
tion-activated (1-to-0, 0-to-1 and both transiton).
The flags that actually generate these interrupts are bit
INT0IFand INT1IF in Register IRQH. When an external
interrupt is generated, the flag that generated it is cleared
by the hardware when the service routine is vectored to
.
Internal bus line
IENH
I-flag is in PSW, it is cleared by “DI”, set by
“EI” instruction.When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by “RETI” instruction, I-flag is set to
Interrupt Enable
Register (Higher byte)
“1” by hardware.
IRQH
7
Release STOP
INT0IF
INT1IF
T0IF
External Int. 0
External Int. 1
IEDS
6
5
4
Timer 0
Timer 1
To CPU
T1IF
I Flag
7
6
Interrupt Master
Enable Flag
ADIF
A/D Converter
WDT
WDTIF
BITIF
Interrupt
Vector
5
BIT
Address
Generator
Interrupt Enable
IRQL
IENL
Register (Lower byte)
Internal bus line
Figure 19-1 Block Diagram of Interrupt Function
The interrupts are controlled by the interrupt master enable
flag I-flag (bit 2 of PSW), the interrupt enable register
(IENH, IENL) and the interrupt request flags (in IRQH,
IRQL) except Power-on reset and software BRK interrupt.
Reset/Interrupt
Symbol Priority Vector Addr.
FFFEH
Hardware Reset
External Interrupt 0 INT0
External Interrupt 1 INT1
Timer 0
Timer 1
A/D Converter
Watch Dog Timer
Basic Interval Timer BIT
RESET
-
FFFAH
FFF8H
FFF6H
FFF4H
FFEAH
FFE8H
FFE6H
1
2
3
4
5
6
7
Interrupt enable registers are shown in Figure 19-2 . These
registers are composed of interrupt enable flags of each in-
terrupt source, these flags determines whether an interrupt
will be accepted or not. When enable flag is "0", a corre-
sponding interrupt source is prohibited. Note that PSW
contains also a master enable bit, I-flag, which disables all
interrupts at once.
Timer 0
Timer 1
A/D C
WDT
Table 19-1 Interrupt Priority
Jan. 2002 ver 2.0
57
HYNIX [ HYNIX SEMICONDUCTOR ]
