GMS81C1102 / GMS81C1202
Interrupt Enable Register High
ADDRESS : E2H
RESET VALUE : 0000----
IENH
IENL
INT0E
INT1E
T0E
T1E
-
-
-
-
-
-
-
-
Interrupt Enable Register Low
ADE WDTE BITE
ADDRESS : E3H
RESET VALUE : 000-----
-
Enables or disables the interrupt individually
If flag is cleared, the interrupt is disabled.
0 : Disable
1 : Enable
Interrupt Request Register High
INT0IF INT1IF T0IF
ADDRESS : E4H
RESET VALUE : 0000----
T1IF
-
-
-
-
-
-
-
-
IRQH
IRQL
Interrupt Request Register Low
ADIF WDTIF BITIF
ADDRESS : E5H
RESET VALUE : 000-----
-
Shows the interrupt occurrence
0 : Not occurred
1 : Interrupt request is occurred
Figure 19-2 Interrupt Enable Registers and Interrupt Request Registers
When an interrupt is occured, the I-flag is cleared and dis-
able any further interrupt, the return address and PSW are
pushed into the stack and the PC is vectored to. Once in the
interrupt service routine the source(s) of the interrupt can
be determined by polling the interrupt request flag bits.
The interrupt request flag bit(s) must be cleared by soft-
ware before re-enabling interrupts to avoid recursive inter-
rupts. The Interrupt Request flags are able to be read and
written.
19.1 Interrupt Sequence
An interrupt request is held until the interrupt is accepted
or the interrupt latch is cleared to "0" by a reset or an in-
struction. Interrupt acceptance sequence requires 8 fOSC (2
µs at fXIN=4MHz) after the completion of the current in-
struction execution. The interrupt service task is terminat-
ed upon execution of an interrupt return instruction
[RETI].
temporarily disabled.
2. Interrupt request flag for the interrupt source accepted is
cleared to "0".
3. The contents of the program counter (return address)
and the program status word are saved (pushed) onto the
stack area. The stack pointer decreases 3 times.
4. The entry address of the interrupt service program is
read from the vector table address and the entry address
is loaded to the program counter.
Interrupt acceptance
1. The interrupt master enable flag (I-flag) is cleared to "0"
to temporarily disable the acceptance of any following
maskable interrupts. When a non-maskable interrupt is
accepted, the acceptance of any following interrupts is
5. The instruction stored at the entry address of the inter-
rupt service program is executed.
58
Jan. 2002 ver 2.0
HYNIX [ HYNIX SEMICONDUCTOR ]
