GMS81C1102 / GMS81C1202
16.2 16-bit Timer/Counter Mode
The Timer register is being run with 16 bits. A 16-bit timer/
counter register T0, T1 are increased from 0000H until it
matches TDR0, TDR1 and then resets to 0000H. The
match output generates Timer 0 interrupt not Timer 1 in-
terrupt.
The clock source of the Timer 0 is selected either internal
or external clock by bit T0CK2, T0CK1 and T0SL0.
In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1
should be set to "1" respectively.
ADDRESS : D0H
RESET VALUE : --000000
-
-
T0CK2
X
T0CK1
X
T0CK0
X
T0CN
X
T0ST
X
TM0
TM1
CAP0
0
-
-
ADDRESS : D2H
RESET VALUE : 00000000
POL
X
T1CK1
T1CK0
T1CN
X
T1ST
X
16BIT
1
PWME
0
CAP1
0
1
1
X : The value "0" or "1" corresponding your operation.
T0CK[2:0]
T0ST
0 : Stop
1 : Start
Edge Detector
1
EC0
T1 ( 8-bit )
T0 ( 8-bit )
CLEAR
MUX
2
÷
4
÷
8
÷
TIMER 0
T0IF
T0CN
32
÷
fxin
INTERRUPT
COMPARATOR
128
÷
512
÷
F/F
2048
÷
TDR1 ( 8-bit )
TDR0 ( 8-bit )
COMP0 PIN
Figure 16-5 16-bit Timer / Counter Mode
16.3 8-bit Compare Output ( 16-bit )
The GMS87C1201 and GMS81C1202 has a function of
Timer Compare Output. To pulse out, the timer match can
goes to port pin( COMP0 ) as shown in Figure 16-2 and
Figure 16-5 . Thus, pulse out is generated by the timer
match. These operation is implemented to pin, RB4/
COMP0/PWM.
wave, and output frequency is same as below equation.
Oscillation Frequency
--------------------------------------------------------------------------------
=
ꢀꢀꢁꢂꢃ
2 × Prescaler Value × (TDR + 1)
In this mode, the bit PWMO of RB function register (RB-
FUNC) should be set to "1", and the bit PWME of timer1
mode register ( TM1 ) should be set to "0".
This pin output the signal having a 50 : 50 duty square
In addition, 16-bit Compare output mode is also available.
16.4 8-bit Capture Mode
The Timer 0 capture mode is set by bit CAP0 of timer
mode register TM0 (bit CAP1 of timer mode register TM1
for Timer 1) as shown in Figure 16-6.
The Timer/Counter register is increased in response inter-
nal or external input. This counting function is same with
normal timer mode, and Timer interrupt is generated when
timer register T0 (T1) increases and matches TDR0
(TDR1).
As mentioned above, not only Timer 0 but Timer 1 can also
be used as a capture mode.
Jan. 2002 ver 2.0
47
HYNIX [ HYNIX SEMICONDUCTOR ]
