GMS81C1102 / GMS81C1202
16.5 16-bit Capture Mode
16-bit capture mode is the same as 8-bit capture, except
that the Timer register is being run will 16 bits.
In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1
should be set to "1" respectively.
The clock source of the Timer 0 is selected either internal
or external clock by bit T0CK2, T0CK1 and T0CK0.
ADDRESS : D0H
RESET VALUE : --000000
-
-
T0CK2
X
T0CK1
X
T0CK0
X
T0CN
X
T0ST
X
CAP0
1
TM0
TM1
-
-
ADDRESS : D2H
RESET VALUE : 00000000
POL
X
CAP1
X
T1CN
X
T1ST
X
16BIT
1
PWME
0
T1CK1
1
T1CK0
1
X : The value "0" or "1" corresponding your operation.
T0CK[2:0]
T0ST
Edge Detector
0 : Stop
1 : Start
1
CLEAR
EC0
fxin
T0 + T1 ( 16-bit )
MUX
2
÷
4
÷
T0CN
TIMER 0
INTERRUPT
T0IF
8
÷
32
÷
COMPARATOR
128
÷
CAPTURE
CDR1
( 8-bit )
TDR1
( 8-bit )
CDR0
( 8-bit )
TDR0
( 8-bit )
512
2048
÷
÷
INT 0
INTERRUPT
INT0IF
INT0
IEDS[1:0]
Figure 16-9 16-bit Capture Mode
16.6 PWM Mode
The GMS81C1202 has a two high speed PWM (Pulse
Width Modulation) functions which shared with Timer1.
And writes duty value to the T1PDR and the
PWM0HR[1:0] same way.
In PWM mode, pin RB4/COMP0/PWM0 outputs up to a
10-bit resolution PWM output. This pin should be defined
as a PWM output by setting "1" bit PWMO in RBFUNC
register.
The T1PDR is configured as a double buffering for glitch-
less PWM output. In Figure 16-10 , the duty data is trans-
fered from the master to the slave when the period data
matched to the counted value. ( i.e. at the beginning of next
duty cycle )
The period of the PWM output is determined by the
T1PPR (PWM0 Period Register) and PWM0HR[3:2]
(bit3,2 of PWM0 High Register) and the duty of the PWM
output is determined by the T1PDR (PWM0 Duty Regis-
ter) and PWM0HR[1:0] (bit1,0 of PWM0 High Register).
PWM Period = [ PWM0HR[3:2]T1PPR ] X Source Clock
PWM Duty = [ PWM0HR[1:0]T1PDR ] X Source Clock
The relation of frequency and resolution is in inverse pro-
portion. Table 16-2 shows the relation of PWM frequency
vs. resolution.
The user writes the lower 8-bit period value to the T1PPR
and the higher 2-bit period value to the PWM0HR[3:2].
50
Jan. 2002 ver 2.0
HYNIX [ HYNIX SEMICONDUCTOR ]
