GMS81C1102 / GMS81C1202
These timers have each 8-bit count register and data regis-
ter. The count register is increased by every internal or ex-
ternal clock input. The internal clock has a prescaler divide
ratio option of 2, 4, 8, 32,128, 512, 2048 (selected by con-
trol bits T0CK2, T0CK1 and T0CK0 of register TM0) and
1, 2, 8 (selected by control bits T1CK1 and T1CK0 of reg-
ister TM1). In the Timer 0, timer register T0 increases
from 00H until it matches TDR0 and then reset to 00H. The
match output of Timer 0 generates Timer 0 interrupt
(latched in T0F bit). As TDRx and Tx register are in same
address, when reading it as a Tx, written to TDRx.
In counter function, the counter is increased every 0-to 1
(rising edge) transition of EC0 pin. In order to use counter
function, the bit RA0 of the RA Direction Register RAIO
is set to "0". The Timer 0 can be used as a counter by pin
EC0 input, but Timer 1 can not.
TDR1
n
n-1
PCP
9
8
7
6
5
4
3
2
1
0
TIME
Interrupt period
= PCP x (n+1)
Timer 1 (T1IF)
Interrupt
interrupt occurs
interrupt occurs
interrupt occurs
Figure 16-3 Counting Example of Timer Data Registers
TDR1
enable
disable
clear & start
stop
TIME
Timer 1 (T1IF)
Interrupt
interrupt occurs
interrupt occurs
T1ST
Start & Stop
T1ST = 1
T1ST = 0
T1CN
Control count
T1CN = 0
T1CN = 1
Figure 16-4 Timer Count Operation
46
Jan. 2002 ver 2.0
HYNIX [ HYNIX SEMICONDUCTOR ]
