GMS81C1102 / GMS81C1202
15. Basic Interval Timer
The GMS81C1202 has one 8-bit Basic Interval Timer that
is free-run, can not stop. Block diagram is shown in Figure
15-1 .The 8-bit Basic interval timer register (BITR) is in-
creased every internal count pulse which is divided by
prescaler. Since prescaler has divided ratio by 8 to 1024,
the count rate is 1/8 to 1/1024 of the oscillator frequency.
As the count overflows from FFH to 00H, this overflow
causes to generate the Basic interval timer interrupt. The
BITF is interrupt request flag of Basic interval timer.
If the STOP instruction executed after writing "1" to bit
RCWDT of CKCTLR, it goes into the internal RC oscillat-
ed watchdog timer mode. In this mode, all of the block is
halted except the internal RC oscillator, Basic Interval
Timer and Watchdog Timer. More detail informations are
explained in Power Saving Function. The bit WDTON de-
cides Watchdog Timer or the normal 7-bit timer
Note: All control bits of Basic interval timer are in CKCTLR
register which is located at same address of BITR
(address ECH). Address ECH is read as BITR, writ-
ten to CKCTLR. Therefore, the CKCTLR can not be
accessed by bit manipulation instruction.
When write "1" to bit BTCL of CKCTLR, BITR register is
cleared to "0" and restart to count-up. The bit BTCL be-
comes "0" after one machine cycle by hardware.
If the STOP instruction executed after writing "1" to bit
WAKEUP of CKCTLR, it goes into the wake-up timer
mode. In this mode, all of the block is halted except the os-
cillator, prescaler ( only fxin÷2048 ) and Timer0.
.
WAKEUP
RCWDT
STOP
BTS[2:0]
8
÷
3
BTCL
Clear
To Watchdog Timer
16
÷
32
÷
÷
8
64
0
fxin
MUX
128
256
512
1024
÷
÷
÷
÷
Basic Interval Timer
Interrupt
BITIF
BITR (8BIT)
1
Internal RC OSC
Figure 15-1 Block Diagram of Basic Interval Timer
Clock Control Register
ADDRESS : ECH
RESET VALUE : -0010111
Bit Manipulation Not Available
-
WAKEUP RCWDT WDTON
Function Description
BTCL
BTS2
BTS1
BTS0
CKCTLR
Basic Interval Timer Clock Selection
000 : fxin
Symbol
8
÷
001 : fxin 16
÷
1: Enables Wake-up Timer
0: Disables Wake-up Timer
WAKEUP
010 : fxin 32
÷
011 : fxin 64
÷
1: Enables Internal RC Watchdog Timer
0: Disables Internal RC Watchdog Time
RCWDT
WDTON
BTCL
100 : fxin 128
÷
101 : fxin 256
÷
1: Enables Watchdog Timer
0: Operates as a 7-bit Timer
110 : fxin 512
÷
111 : fxin 1024
÷
1: BITR is cleared and BTCL becomes "0" automatically
after one machine cycle, and BITR continue to count-up
Figure 15-2 CKCTLR : Clock Control Register
Jan. 2002 ver 2.0
43
HYNIX [ HYNIX SEMICONDUCTOR ]
