Chapter 4. Peripheral Hardware
Internal Data Bus
<00D5H>
<00D6H>
<00D3H> <00D4H>
<00D5H>
<00D6H>
R/W
<00D0H>
TIMER0
HM
DATA
REG
TIMER0
HL
DATA
REG
TIMER0 TIMER0
TIMER0
COUNT
REG
H
TIMER0 L
COUNT
REG
LM
DATA
REG
LL
DATA
REG
7
6
5
4
3
2
1
0
TM0
DATA READ
SINGLE/
MODULO-N
SELECTION
16 16
MUX
16
PS0
PS1
PS2
PS3
PS4
PS5
PS11
EC
CK
Int.
Gen.
MUX
T0 COUNTER
(16 BIT)
M
U
X
IFT0
D
E
L
Clear
A
Y
EDGE
SELECTION
INT2
T0INT
OUTPUT GEN.
T0 OUT
Fig. 4.7 Block Diagram of Timer0
4 - 13