RFM70 V1.0
7 Register Map
There are two register banks, which can be toggled by SPI command “ACTIVATE” followed
with
0x53 byte, and bank status can be read from Bank0_REG7 [7].
7.1 Register Bank 0
Address
(Hex)
Reset
Value
Mnemonic
Bit
Type
Description
00
CONFIG
Configuration Register
Reserved
7
6
0
0
R/W
R/W
Only '0' allowed
Mask interrupt caused by RX_DR
MASK_RX_DR
MASK_TX_DS
MASK_MAX_RT
1: Interrupt not reflected on the IRQ pin
0: Reflect RX_DR as active low interrupt
on the IRQ pin
Mask interrupt caused by TX_DS
1: Interrupt not reflected on the IRQ pin
0: Reflect TX_DS as active low interrupt on
the IRQ pin
Mask interrupt caused by MAX_RT
1: Interrupt not reflected on the IRQ pin
0: Reflect MAX_RT as active low interrupt
on the IRQ pin
5
4
0
0
R/W
R/W
Enable CRC. Forced high if one of the bits
in the EN_AA is high
CRC encoding scheme
EN_CRC
CRCO
3
2
1
0
R/W
R/W
'0' - 1 byte
'1' - 2 bytes
PWR_UP
PRIM_RX
1
0
0
0
R/W
R/W
1: POWER UP, 0:POWER DOWN
RX/TX control,
1: PRX, 0: PTX
01
EN_AA
Enable „Auto Acknowledgment‟ Function
Reserved
7:6
5
4
3
2
00
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Only '00' allowed
ENAA_P5
ENAA_P4
ENAA_P3
ENAA_P2
ENAA_P1
ENAA_P0
Enable auto acknowledgement data pipe 5
Enable auto acknowledgement data pipe 4
Enable auto acknowledgement data pipe 3
Enable auto acknowledgement data pipe 2
Enable auto acknowledgement data pipe 1
Enable auto acknowledgement data pipe 0
1
0
1
1
02
EN_RXADDR
Reserved
ERX_P5
ERX_P4
ERX_P3
ERX_P2
ERX_P1
ERX_P0
Enabled RX Addresses
Only '00' allowed
7:6
5
4
3
2
00
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Enable data pipe 5.
Enable data pipe 4.
Enable data pipe 3.
Enable data pipe 2.
Enable data pipe 1.
Enable data pipe 0.
1
0
1
1
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