HI-8685, HI-8686
TIMING DIAGRAMS
ARINC Data Bits
29 30 31
Word Gap
4 Bit Periods Min.
28
32
1
2
+10V
0V
VDIFF
RINA - RINB
-10V
DERIVED DATA
DERIVED CLOCK
FIGURE 3 - RECEIVER INPUT TIMING FOR ARINC 429
ARINC Data Bits
29 30 31
Word Gap
4 Bit Periods Min.
28
32
1
2
+5V
0V
TESTA
+5V
0V
TESTB
DERIVED DATA
DERIVED CLOCK
FIGURE 4 - TEST INPUT TIMING FOR ARINC 429
32nd
ARINC bit
DERIVED DATA
tDRDY
tRDYCLR
DATA RDY
READ
tRDPW
tRR
1st 16-bits
2nd 16-bits
tRD
tFD
D0 - D15
VALID
VALID
FIGURE 5 - RECEIVER PARALLEL DATABUS TIMING
HOLT INTEGRATED CIRCUITS
5