HI-3582, HI-3583
FUNCTIONAL DESCRIPTION (cont.)
RETRIEVING DATA
RECEIVER PARITY
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). Depending upon the state of control
register bits CR2-CR11, the received ARINC 32-bit word is then
checked for correct decoding and label matching before being
loaded into the 32 x 32 receive FIFO. ARINC words which do not
meet the necessary 9th and 10th ARINC bit or label matching are
ignored and are not loaded into the receive FIFO. The following
table describes this operation.
The 32nd bit of received ARINC words stored in the receive FIFO
is used as a Parity Flag indicating whether good Odd parity is
received from the incoming ARINC word.
Odd Parity Received
The parity bit is reset to indicate correct parity was received
and the resulting word is written to the receive FIFO.
Even Parity Received
The receiver sets the 32nd bit to a “1”, indicating a parity error
and the resulting word is then written to the receive FIFO.
CR2(3) ARINC word CR6(9) ARINC word
FIFO
matches
label
bits 9,10
match
CR7,8 (10,11)
Therefore, the 32nd bit retrieved from the receiver FIFO will always
be “0” when valid (odd parity)ARINC 429 words are received.
0
1
1
0
0
1
1
1
1
X
No
Yes
X
0
0
0
1
1
1
1
1
1
X
X
Load FIFO
Ignore data
Load FIFO
Ignore data
Load FIFO
Ignore data
Ignore data
Ignore data
Load FIFO
X
No
Yes
No
Yes
No
Yes
X
Yes
No
No
Yes
HOLT INTEGRATED CIRCUITS
5
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
