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HI-3583PQMF-10 参数 Datasheet PDF下载

HI-3583PQMF-10图片预览
型号: HI-3583PQMF-10
PDF下载: 下载PDF文件 查看货源
内容描述: ARINC 429 3.3V终端IC [ARINC 429 3.3V Terminal IC]
分类和应用: 微控制器和处理器串行IO控制器通信控制器外围集成电路数据传输时钟
文件页数/大小: 18 页 / 126 K
品牌: HOLTIC [ HOLT INTEGRATED CIRCUITS ]
 浏览型号HI-3583PQMF-10的Datasheet PDF文件第1页浏览型号HI-3583PQMF-10的Datasheet PDF文件第3页浏览型号HI-3583PQMF-10的Datasheet PDF文件第4页浏览型号HI-3583PQMF-10的Datasheet PDF文件第5页浏览型号HI-3583PQMF-10的Datasheet PDF文件第6页浏览型号HI-3583PQMF-10的Datasheet PDF文件第7页浏览型号HI-3583PQMF-10的Datasheet PDF文件第8页浏览型号HI-3583PQMF-10的Datasheet PDF文件第9页  
HI-3582, HI-3583  
PIN DESCRIPTIONS  
SIGNAL  
VDD  
FUNCTION  
POWER  
INPUT  
INPUT  
INPUT  
INPUT  
OUTPUT  
OUTPUT  
OUTPUT  
OUTPUT  
OUTPUT  
OUTPUT  
INPUT  
INPUT  
INPUT  
I/O  
DESCRIPTION  
+3.3V power supply pin  
RIN1A  
RIN1B  
RIN2A  
RIN2B  
D/R1  
FF1  
ARINC receiver 1 positive input  
ARINC receiver 1 negative input  
ARINC receiver 2 positive input  
ARINC receiver 2 negative input  
Receiver 1 data ready flag  
FIFO full Receiver 1  
HF1  
FIFO Half full, Receiver 1  
D/R2  
FF2  
Receiver 2 data ready flag  
FIFO full Receiver 2  
HF2  
FIFO Half full, Receiver 2  
SEL  
Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2)  
EN1  
Data Bus control, enables receiver 1 data to outputs  
EN2  
Data Bus control, enables receiver 2 data to outputs if EN1 is high  
BD15  
BD14  
BD13  
BD12  
BD11  
BD10  
BD09  
BD08  
BD07  
BD06  
GND  
BD05  
BD04  
BD03  
BD02  
BD01  
BD00  
PL1  
Data Bus  
I/O  
Data Bus  
I/O  
Data Bus  
I/O  
Data Bus  
I/O  
Data Bus  
I/O  
Data Bus  
I/O  
Data Bus  
I/O  
Data Bus  
I/O  
Data Bus  
I/O  
Data Bus  
POWER  
I/O  
0 V  
Data Bus  
I/O  
Data Bus  
I/O  
Data Bus  
I/O  
Data Bus  
I/O  
Data Bus  
I/O  
Data Bus  
INPUT  
INPUT  
OUTPUT  
Latch enable for byte 1 entered from data bus to transmitter FIFO.  
Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow PL1.  
PL2  
TX/R  
Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high  
after transmission and FIFO empty.  
HFT  
FFT  
OUTPUT  
OUTPUT  
POWER  
OUTPUT  
OUTPUT  
POWER  
INPUT  
Transmitter FIFO Half Full  
Transmitter FIFO Full  
V-  
-9.5V to -10.5V  
TXAOUT  
TXBOUT  
V+  
Line driver output - A side  
Line driver output - B side  
+9.5V to +10.5V  
ENTX  
CWSTR  
RSR  
Enable Transmission  
INPUT  
Clock for control word register  
Read Status Register if SEL=0, read Control Register if SEL=1  
Master Clock input  
INPUT  
CLK  
INPUT  
TX CLK  
MR  
OUTPUT  
INPUT  
Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80.  
Master Reset, active low  
TEST  
INPUT  
Disable Transmitter output if high (pull-down)  
HOLT INTEGRATED CIRCUITS  
2
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