HI-3582, HI-3583
FUNCTIONAL DESCRIPTION (cont.)
The HI-3582/HI-3583 guarantee recognition of these levels with a
common mode Voltage with respect to GND less than 4V for the
worst case condition (3.0V supply and 13V signal level).
ARINC 429 DATA FORMAT
Control register bit CR15 is used to control how individual bits in the
received or transmitted ARINC word are mapped to the HI-3582/
HI-3583 data bus during data read or write operations. The
following table describes this mapping:
The tolerances in the design guarantee detection of the above
levels, so the actual acceptance ranges are slightly larger. If the
ARINC signal is out of the actual acceptance ranges, including the
nulls, the chip rejects the data.
BYTE 1
DATA
BUS
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
RECEIVER LOGIC OPERATION
Figure 2 shows a block diagram of the logic section of each receiver.
BIT TIMING
ARINC
BIT
13 12 11 10
9
31 30 32
1
2
3
4
5
6
7
8
CR15=0
ARINC
BIT
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
The ARINC 429 specification contains the following timing specifi-
cation for the received data:
CR15=1
HIGH SPEED
LOW SPEED
BIT RATE
PULSE RISE TIME 1.5 0.5 µsec
PULSE FALL TIME 1.5 0.5 µsec
100K BPS 1% 12K -14.5K BPS
BYTE 2
10 5 µsec
10 5 µsec
5 µsec 5% 34.5 to 41.7 µsec
DATA
BUS
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PULSE WIDTH
ARINC
BIT
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
The HI-3582/HI-3583 accept signals that meet these specifica-
tions and rejects signals outside the tolerances. The way the logic
operation achieves this is described below:
CR15=0
ARINC
BIT
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
CR15=1
1. Key to the performance of the timing checking logic is an
accurate 1MHz clock source. Less than 0.1% error is recom-
mended.
THE RECEIVERS
2. The sampling shift registers are 10 bits long and must
show three consecutive Ones, Zeros or Nulls to be consid-
ered valid data. Additionally, for data bits, the One or Zero in
the upper bits of the sampling shift registers must be followed
by a Null in the lower bits within the data bit time. For a Null in
the word gap, three consecutive Nulls must be found in both
the upper and lower bits of the sampling shift register. In this
manner the minimum pulse width is guaranteed.
ARINC BUS INTERFACE
Figure 1 shows the input circuit for each receiver. The ARINC 429
specification requires the following detection levels:
STATE
DIFFERENTIALVOLTAGE
ONE
NULL
ZERO
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
3. Each data bit must follow its predecessor by not less than
8 samples and no more than 12 samples. In this manner the
bit rate is checked. With exactly 1MHz input clock frequency,
the acceptable data bit rates are as follows:
vDD
DIFFERENTIAL
AMPLIFIERS
COMPARATORS
HIGH SPEED LOW SPEED
DATA BIT RATE MIN
DATA BIT RATE MAX
83K BPS
125K BPS
10.4K BPS
15.6K BPS
RIN1A
OR
RIN2A
ONES
NULL
GND
4. The Word Gap timer samples the Null shift register every
10 input clocks (80 for low speed) after the last data bit of a
valid reception. If the Null is present, the Word Gap counter
is incremented. A count of 3 will enable the next reception.
vDD
ZEROES
RIN1B
OR
RIN2B
GND
FIGURE 1. ARINC RECEIVER INPUT
HOLT INTEGRATED CIRCUITS
4
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
