HI-3582, HI-3583
FUNCTIONAL DESCRIPTION
CONTROL WORD REGISTER
STATUS REGISTER
The HI-3582/HI-3583 contain a 9-bit status register which can be
interrogated to determine the status of the ARINC receivers, data
FIFOs and transmitter. The contents of the status register are
output on BD00 - BD08 when the RSR pin is taken low and
SEL = 0. Unused bits are output as Zeros. The following table
defines the status register bits.
The HI-3582/HI-3583 contain a 16-bit control register which is
used to configure the device. The control register bits CR0 - CR15
are loaded from BD00 - BD15 when CWSTR is pulsed low. The
control register contents are output on the databus when SEL = 1
and RSR is pulsed low. Each bit of the control register has the
following function:
SR
Bit
CR
Bit
FUNCTION
STATE
DESCRIPTION
FUNCTION
STATE
DESCRIPTION
CR0
Receiver 1
Data clock
Select
0
1
0
1
Data rate = CLK/10
Data rate = CLK/80
Normal operation
SR0
Data ready
(Receiver 1)
0
1
Receiver 1 FIFO empty
Receiver 1 FIFO contains valid data
Resets to zero when all data has
been read. D/R1 pin is the inverse of
this bit
CR1
Label Memory
Read / Write
Load 16 labels using PL1 / PL2
Read 16 labels using EN1 / EN2
SR1
SR2
SR3
SR4
SR5
FIFO half full
(Receiver 1)
0
1
Receiver 1 FIFO holds less than 16
words
CR2
CR3
CR4
CR5
Enable Label
Recognition
(Receiver 1)
0
1
0
1
0
1
0
Disable label recognition
Enable label recognition
Disable Label Recognition
Enable Label recognition
Transmitter 32nd bit is data
Transmitter 32nd bit is parity
Receiver 1 FIFO holds at least 16
words. HF1 pin is the inverse of
this bit.
Enable Label
Recognition
(Receiver 2)
FIFO full
(Receiver 1)
0
1
Receiver 1 FIFO not full
Receiver 1 FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period. FF1 pin is
the inverse of this bit
Enable
32nd bit
as parity
Self Test
The transmitter’s digital
outputs are internally connected
to the receiver logic inputs
Data ready
(Receiver 2)
0
1
Receiver 2 FIFO empty
Receiver 2 FIFO contains valid data
Resets to zero when all data has
been read. D/R2 pin is the inverse of
this bit
1
0
1
Normal operation
CR6
Receiver 1
decoder
Receiver 1 decoder disabled
FIFO half full
(Receiver 2)
0
1
Receiver 2 FIFO holds less than 16
words
ARINC bits 9 and 10 must match
CR7 and CR8
Receiver 2 FIFO holds at least 16
words. HF2 pin is the inverse of
this bit.
CR7
CR8
CR9
-
-
-
-
If receiver 1 decoder is enabled,
the ARINC bit 9 must match this bit
If receiver 1 decoder is enabled,
the ARINC bit 10 must match this bit
FIFO full
(Receiver 2)
0
1
Receiver 2 FIFO not full
Receiver 2 FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period. FF2 pin is
the inverse of this bit
Receiver 2
Decoder
0
1
Receiver 2 decoder disabled
ARINC bits 9 and 10 must match
CR10 and CR11
SR6 Transmitter FIFO
empty
0
1
0
1
Transmitter FIFO not empty
Transmitter FIFO empty.
Transmitter FIFO not full
CR10
CR11
CR12
-
-
-
-
If receiver 2 decoder is enabled,
the ARINC bit 9 must match this bit
If receiver 2 decoder is enabled,
the ARINC bit 10 must match this bit
SR7 Transmitter FIFO
full
Transmitter FIFO full. FFT pin is the
inverse of this bit.
Invert
Transmitter
parity
0
1
0
1
0
1
0
1
Transmitter 32nd bit is Odd parity
Transmitter 32nd bit is Even parity
Data rate=CLK/10, O/P slope=1.5us
Data rate=CLK/80, O/P slope=10us
Data rate=CLK/10
SR8 Transmitter FIFO
half full
0
1
Transmitter FIFO contains less than
16 words
CR13
CR14
CR15
Transmitter
data clock
select
Transmitter FIFO contains at least
16 words.HFT pin is the
inverse of this bit.
Receiver 2
data clock
select
Data rate=CLK/80
Data
format
Scramble ARINC data
Unscramble ARINC data
HOLT INTEGRATED CIRCUITS
3
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
