HI-3200, HI-3201
COPYERR
CTXRDY
PENDING INTERRUPT REGISTER
(Address 0x800A)
7
6
5
4
3
2
1
0
LSB
MSB
The MINTwill be asserted when any of the bits in this register are set.
Bit Name
R/W Default Description
7
6
5
4
3
2
COPYERR
R
R
R
R
R
R
0
0
0
0
0
0
EE copy error. RAM - EEPROM mismatch
Auto-inititailization RAM read error
Auto-initialization checksum fail
AUTOERR
CHKERR
RAMFAIL
FLAG
Power-On Reset RAM Integrity Check fail
Logical OR ofARINC 429 Receive FIFO FLAG signals
ATXRDY
ARINC 429 Host TX ready. Used with Host SPI op-code 100101TT (see Table 1). Interrupt
when any of the fourARINC 429 transmitters are ready for the next 32-bit word from the host
1
0
CANRX
R
R
0
0
CAN Bus received frame Interrupt
CTXRDY
CAN Host Tx ready. Used with host SPI opcode 10010000. Interrupt when ready for next CAN
frame from host.
COPYERR
CTXRDYIE
PENDING INTERRUPT ENABLE REGISTER
(Address 0x8034)
7
6
5
4
3
2
1
0
LSB
MSB
Bit Name
R/W Default Description
7
6
5
4
3
2
1
0
COPYERR
R
R
1
1
1
1
0
0
0
0
COPYERR is not maskable
AUTOERR is not maskable
CHKERR is not maskable
RAMFAILis not maskable
AUTOERR
CHKERR
RAMFAIL
FLAGIE
R
R
R/W
R/W
R/W
R/W
MINTpin is asserted if this bit is a “1” and the Pending Interrupt Register FLAG bit is set
MINTpin is asserted if this bit is a “1” and the Pending Interrupt RegisterATXRDYbit is set
MINTpin is asserted if this bit is a “1” and the Pending Interrupt Register CANRX bit is set
MINTpin is asserted if this bit is a “1” and the Pending Interrupt Register CTXRDYbit is set
ATXRDYIE
CANRXIE
CTXRDYIE
HOLT INTEGRATED CIRCUITS
42
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
