HI-3200, HI-3201
INTERRUPT HANDLING
The HI-3200 includes a simple, user-selectable Interrupt
Handler. Two types of Interrupt are possible - Message
Event Driven (ARINC 429 or CAN Bus), and Fault Driven.
CAN Bus Interrupts
An interrupt is generated on receipt of a CAN frame
whose corresponding Filter and Interrupt look-up table
bits are a “1”. The CANRX bit is set in the Pending
Interrupt Register PIR, and the filter number which
accepted the CAN frame is written to the CAN Interrupt
Address Register CIAR. For example, if filter # 0xA1
accepts the frame, the value 0xA1 is written to CIAR.
ARINC 429 Receive Interrupts
As described earlier, the user can elect to generate an
interrupt upon receipt of an ARINC 429 message on any
combination of the eight available channels and for any
of the possible 256 label byte (ARINC message bits 1-8)
values. Interrupts are enabled when the ARINC 429 Rx
Interrupt look-up bit is a “1”.
The Interrupt output, MINT, is asserted if the Interrupt
Mask Register CANRX bit is a “1”.
A special SPI Instruction allows the user to extract the
received frame information from the CAN receive
memory without having to first determine its sixteen-bit
absolute address. The CIAR value is used as a relative
address pointer.
When a message arrives that is flagged to generate an
Interrupt, that channel’s bit is set in the ARINC 429
Receiver Pending Interrupt Register APIR. The ARINC
429 Interrupt Address Register (AIAR) for that channel is
updated with the ARINC 429 8-bit label value.
For example, if ARINC Receive channel 7 is enabled for
Interrupts when messages with ARINC label 0xD4 arrive,
then on receipt of such a message, APIR bit 7 is set to a
“1” and the value 0xD4 is written to AIAR7.
Fault Interrupts
There are four fault Interrupt bits in the PIR. Fault
Interrupts are not maskable, and their Interrupt Mask bits
are fixed at a “1”.
If the corresponding bit in the ARINC 429 Receive
Interrupt Mask Register is a “1” the AINT interrupt output
will go high and stay high until the AACK input pin is
driven high. Driving AACK high, causes the AINT pin to
return to zero.
COPYERR is set when the HI-3200 detects a mismatch
between RAM and EEPROM after attempting to program
the Auto-initialization EEPROM.
AUTOERR is set when the Auto-Initialization EEPROM
read verification cycle detects a mismatch between the
on-chip memory and EEPROM following auto-
initialization.
A special Indexed SPI read instruction is available to
allow the host to efficiently retrieve ARINC 429 messages
which have Interrupts Enabled (see SPI instruction set
section).
CHKERR is set when an auto-initialization checksum
error is detected.
Note that if AACK is tied high permanently, the AINT pin
will go high for approximately 1 us before returning to
zero. A host CPU read of the APIR register reads the
current value and resets APIR to 0x00.
The RAMFAIL bit is set if the Built-In Self Test sequence
fails.
HOLT INTEGRATED CIRCUITS
41
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
