HI-3200, HI-3201
bus configuration registers (CANBTR0, CANBTR1) is
transferred to the HI-3110 and other HI-3110 reset and
initialization tasks are performed.
5 Enable SPI By-Pass
In Mode 6, the host CPU SPI interface completely by-
passes the HI-3200, and all communication is directed to
the HI-3110 SPI bus such that the user may directly
access registers within the HI-3110. This “by-pass’ mode
is intended as an aid to debugging only and is not
recommended in the final system design implementation.
The following values are written to the HI-3110 registers
in the sequence outlined below.
Write 0x88 to HI-3110 CTRL1 Register
Write Register 0x8030 to HI-3110 BTR0 Register
Write Register 0x8031 to HI-3110 BTR1 Register
Write 0x40 to HI-3110 STATE Register
Write 0x65 to HI-3110 GPINE Register
Write 0x07 to HI-3110 CTRL0 Register
By-pass mode is exited at the first rising edge of the RUN
pin. Further toggling of the RUN pin will not re-engage
the by-pass mode. Since the host does not have access
to internal HI-3200 registers prior to RUN going high, the
user must first initialize these registers prior to entering
Mode 6.
The HI-3200 communicates with the HI-3110 over its
dedicated SPI bus.
6. HI-3110 Initialize
Following HI-3110 initialization, the HI-3200 enters the
ACTIVE state and bus message processing begins.
In Modes 0 through 5, as soon as the RUN input is
transitioned from low to high, the contents of the CAN
HOLT INTEGRATED CIRCUITS
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HOLTIC [ HOLT INTEGRATED CIRCUITS ]
