HI-3200, HI-3201
TXIE0
A
X
X
6
X
5
X
4
ARINC 429 TX READY INT ENABLE
(Address 0x8035)
7
3
2
1
0
LSB
MSB
Bit Name
R/W Default Description
7
6
5
4
3
-
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Not Used
Not Used
Not Used
Not Used
-
-
-
ATXIE3
Setting this bit generates an interrupt when ARINC 429 Transmitter 3 is ready to receive the
next 32-bit word from the host for transmission. The ATXRDY bit in the Pending
Interrupt Register will be set and the MINT pin will be asserted if theATXRDYIE bit is set in the
Pending Interrupt Enable Register.
2
1
0
ATXIE2
ATXIE1
ATXIE0
R/W
R/W
R/W
0
0
0
Setting this bit generates an interrupt when ARINC 429 Transmitter 2 is ready to receive the
next 32-bit word from the host for transmission. The ATXRDY bit in the Pending
Interrupt Register will be set and the MINT pin will be asserted if theATXRDYIE bit is set in the
Pending Interrupt Enable Register.
Setting this bit generates an interrupt when ARINC 429 Transmitter 1 is ready to receive the
next 32-bit word from the host for transmission. The ATXRDY bit in the Pending
Interrupt Register will be set and the MINT pin will be asserted if theATXRDYIE bit is set in the
Pending Interrupt Enable Register.
Setting this bit generates an interrupt when ARINC 429 Transmitter 0 is ready to receive the
next 32-bit word from the host for transmission. The ATXRDY bit in the Pending
Interrupt Register will be set and the MINT pin will be asserted if theATXRDYIE bit is set in the
Pending Interrupt Enable Register.
CIAR
CAN INTERRUPT ADDRESS REGISTER
(Address 0x800B)
7
6
5
4
3
2
1
0
LSB
MSB
HOLT INTEGRATED CIRCUITS
43
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
