HI-3200, HI-3201
RESET AND START-UP
OPERATION
After power-on, the HI-3200 is in an undefined state. The
RESET pin must be taken high to begin device
initialization. The RESET pin may be asserted at any
time. Taking RESET high immediately stops all execution
and sets the READY output low indicating that the part is
in the reset state.
2. Clear Data Memory
In Modes 0, 1, 2, 3, 5, 6, and 7, the HI-3200 automatically
clears all memory locations in the address range 0x0000
to 0x33FF. This is the space reserved for ARINC 429 and
CAN message data. Configuration tables and HI-3200
registers are not affected.
On the falling edge of RESET, the HI-3200 samples the
state of the MODE2-0 input pins. This is the only
occasion these inputs are sampled. The state of the
MODE pins determines one of eight possible initialization
sequences (Mode 0 through Mode 7) as shown in the
following diagram. These eight initialization modes allow
the user to customize the start-up configuration of the
device.
3. Initialize Registers and Clear all memory
In addition to clearing data memory (0x0000 to 0x33FF),
Modes 0, 1, 2, and 3 also clear all configuration and look-
up tables (0x3400 to 0x7FFF) as well as setting all
registers (0x8000 to 0x807F) to their default states. All
registers default to zero unless otherwise noted.
Once the initialization is complete, the device enters the
Idle State when the ready pin goes high. In Idle State, the
host CPU may communicate with the HI-3200 memory
and registers using the host CPU SPI link. Note that
when Mode 6 is selected, the host CPU SPI by-passes
the HI-3200 and instead communicates directly with the
HI-3110 CAN controller, if used. When in the Idle State,
The HI-3200 does not transmit or receive any messages
on either the ARINC 429 buses or the CAN bus.
4. Auto-Initialize from EEPROM
The contents of the Auto-Initialization EEPROM are
copied into the HI-3200 memory and registers via the
EEPROM SPI interface. The part verifies the integrity of
the data transfer from the EEPROM by running through a
byte-by-byte compare routine and a checksum validation.
If a compare error is detected, the AUTOERR bit is set in
the Pending Interrupt Register, the MINT output is
asserted, the location of the error is captured in the
AUTO-INIT FAIL ADDRESS registers 0x8073 (Auto-Init
Fail LS address) and 0x8074 (Auto-Init Fail MS address)
and the part enters the Safe state. If a checksum error is
detected, the CHKERR bit is set in the Pending Interrupt
Register, the MINT output is asserted and the part enters
the Safe state. The AUTOERR and the CHKERR
interrupts are not maskable.
To begin data bus operation, the user must transition the
RUN input from a low to high state. Immediately following
the rising edge of RUN, the HI-3200 configures the HI-
3110 CAN controller, if used, according to the MODE
selection. The part then enters the Active State and bus
message processing begins.
During initialization, various device configuration tasks
are performed according to the Mode selection set at the
MODE2:0 input pins. The available options are:
Once initialization is complete, the part enters the Idle
state. The host CPU may read and write HI-3200 internal
memory and registers in Modes 0, 1, 2, 3, 4, 5, and 7. If
not using the auto-initizarion feature, the host CPU
should configure the device at this time.
1. RAM Integrity Check
In Modes 2 and 3, the HI-3200 performs a RAM integrity
check. A read/write check is performed on the entire
RAM space. An incrementing pattern is written to
sequential RAM locations then this pattern is read and
verified. Each RAM location is re-written with the 1s
complement of its current contents then this pattern is
read and verified. The incrementing pattern followed by
its 1s complement ensures that each RAM location can
store both a 1 and 0 state. If the RAM integrity check
fails, the MINT pin is asserted and the Pending Interrupt
Register RAMFAIL bit is set. The part enters the “Safe”
state, in which the HI-3200 is able to accept and respond
to Host CPU SPI Instructions, but cannot enter Normal
Operating mode until the RESET input is taken high to
repeat the initialization sequence. The RAMFAIL Interrupt
is not maskable.
HOLT INTEGRATED CIRCUITS
38
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
