HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
·
CTRL0 Register - HT48R01B/HT48R02B/HT48R01N/HT48R02N
Bit
Name
R/W
7
6
PFDCS
R/W
0
5
4
3
2
PFDC
R/W
0
1
LXTLP
R/W
0
0
CLKMOD
R/W
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
0
Bit 7
unimplemented, read as ²0²
Bit 6
PFDCS: PFD clock source
0: timer0
1: timer1
Bit 5~3
Bit 2
unimplemented, read as ²0²
PFDC: I/O or PFD
0: I/O
1: PFD
Bit 1
Bit 0
LXTLP: LXT oscillator low power control function
0: LXT Oscillator quick start-up mode
1: LXT Oscillator Low Power Mode
CLKMOD: system clock mode selection.
0: High speed - HIRC used as system clock
1: Low speed - LXT used as system clock, HIRC oscillator stopped.
These selections are only valid if the oscillator configuration options
have selected the HIRC+LXT.
·
CTRL1 Register
Bit
7
6
INTEG0
R/W
0
5
TBSEL1
R/W
0
4
TBSEL0
R/W
0
3
2
1
0
Name
R/W
INTEG1
R/W
1
WDTEN3 WDTEN2 WDTEN1 WDTEN0
R/W
1
R/W
0
R/W
1
R/W
0
POR
Bit 7, 6
INTEG1, INTEG0: External interrupt edge type
00: disable
01: rising edge trigger
10: falling edge trigger
11: dual edge trigger
Bit 5, 4
TBSEL1, TBSEL0: Time base period selection
00: 210 ´ (1/fTP
01: 211 ´ (1/fTP
10: 212 ´ (1/fTP
11: 213 ´ (1/fTP
)
)
)
)
Bit 3~0
Note:
WDTEN3, WDTEN2, WDTEN1, WDTEN0: WDT function enable
1010: WDT disabled
Other values: WDT enabled - Recommended value is 0101
If the ²watchdog timer enable² configuration option is selected, then the watchdog timer will
always be enabled and the WDTEN3~WDTEN0 control bits will have no effect.
The WDT is only disabled when both the WDT configuration option is disabled and when bits
WDTEN3~WDTEN0=1010.
The WDT is enabled when either the WDT configuration option is enabled or when bits
WDTEN3~WDTEN0¹1010.
Rev.1.10
19
February 12, 2010
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
