HT48R50A-1/HT48C50-1
The I/O functions of PB0/PB1 are shown below.
PB0 I/O
I
I
I
O
I
O
I
O
I
O
O
O
O
B
C
0
O
O
B
C
1
O
O
B
B
0
O
O
B
B
1
PB1 I/O
O
x
PB0 Mode
PB1 Mode
PB0 Data
x
x
x
x
I
C
x
B
x
0
x
0
I
B
x
1
x
B
I
C
C
x
C
D
x
D0
D1
D0
D1
PB1 Data
D
I
D
0
D
B
D
x
x
PB0 Pad Status
PB1 Pad Status
D
I
0
B
B
I
D
D
0
Note:
²I² input, ²O² output, ²D, D0, D1² data,
²B² buzzer option, BZ or BZ, ²x² don't care
²C² CMOS output
The PG0 is pin-shared with INT.
The LVR includes the following specifications:
·
The low voltage (0.9V~VLVR) has to remain in its origi-
nal state for longer than 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and will
not perform a reset function.
In case of ²Internal RC+I/O² system oscillator, the PG1
and PG2 are pin-shared with OSC1 and OSC2 pins.
Once the ²Internal RC+I/O² mode is selected, the PG1
and PG2 can be used as general purpose I/O lines. Oth-
erwise, the pull-high resistors and I/O functions of PG1
and PG2 will be disabled.
·
The LVR uses an ²OR² function with the external RES
signal to perform a chip reset.
The relationship between VDD and VLVR is shown below.
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
V
D
D
V
O P R
5
.
5
V
5
.
5
V
Low Voltage Reset - LVR
V
L
V
R
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as when changing a battery, the LVR
will automatically reset the device internally.
3
.
0
V
2
.
2
V
0
.
9
V
V
OPR is the voltage range for proper chip opera-
Note:
tion at 4MHz system clock.
V
D
D
5
.
5
V
L
V
R
D
e
t
e
c
t
V
o
l
t
a
g
e
V
L
V
R
0
.
9
0
V
V
R
e
s
e
t
S
i
g
n
a
l
R
e
s
e
t
N
o
r
m
a
l
O
p
e
r
a
t
i
o
n
R
e
s
e
t
*
1
*
2
Low Voltage Reset
Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024
system clock pulses before starting the normal operation.
*2: Since low voltage has to be maintained its original state for longer than 1ms, therefore a 1ms delay
enters the reset mode.
Rev. 2.01
17
January 9, 2009
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
