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HT48R50A-1_09 参数 Datasheet PDF下载

HT48R50A-1_09图片预览
型号: HT48R50A-1_09
PDF下载: 下载PDF文件 查看货源
内容描述: I / O型8位MCU [I/O Type 8-Bit MCU]
分类和应用:
文件页数/大小: 39 页 / 280 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
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HT48R50A-1/HT48C50-1  
Bit Operations  
Other Operations  
The ability to provide single bit operations on Data Mem-  
ory is an extremely flexible feature of all Holtek  
microcontrollers. This feature is especially useful for  
output port bit programming where individual bits or port  
pins can be directly set high or low using either the ²SET  
[m].i² or ²CLR [m].i² instructions respectively. The fea-  
ture removes the need for programmers to first read the  
8-bit output port, manipulate the input data to ensure  
that other bits are not changed and then output the port  
with the correct new data. This read-modify-write pro-  
cess is taken care of automatically when these bit oper-  
ation instructions are used.  
In addition to the above functional instructions, a range  
of other instructions also exist such as the ²HALT² in-  
struction for Power-down operations and instructions to  
control the operation of the Watchdog Timer for reliable  
program operations under extreme electric or electro-  
magnetic environments. For their relevant operations,  
refer to the functional related sections.  
Instruction Set Summary  
The following table depicts a summary of the instruction  
set categorised according to function and can be con-  
sulted as a basic instruction reference using the follow-  
ing listed conventions.  
Table Read Operations  
Table conventions:  
Data storage is normally implemented by using regis-  
ters. However, when working with large amounts of  
fixed data, the volume involved often makes it inconve-  
nient to store the fixed data in the Data Memory. To over-  
come this problem, Holtek microcontrollers allow an  
area of Program Memory to be setup as a table where  
data can be directly stored. A set of easy to use instruc-  
tions provides the means by which this fixed data can be  
referenced and retrieved from the Program Memory.  
x: Bits immediate data  
m: Data Memory address  
A: Accumulator  
i: 0~7 number of bits  
addr: Program memory address  
Mnemonic  
Arithmetic  
Description  
Cycles Flag Affected  
ADD A,[m]  
ADDM A,[m]  
ADD A,x  
Add Data Memory to ACC  
1
1Note  
1
Z, C, AC, OV  
Z, C, AC, OV  
Z, C, AC, OV  
Z, C, AC, OV  
Z, C, AC, OV  
Z, C, AC, OV  
Z, C, AC, OV  
Z, C, AC, OV  
Z, C, AC, OV  
Z, C, AC, OV  
C
Add ACC to Data Memory  
Add immediate data to ACC  
ADC A,[m]  
ADCM A,[m]  
SUB A,x  
Add Data Memory to ACC with Carry  
1
1Note  
Add ACC to Data memory with Carry  
Subtract immediate data from the ACC  
Subtract Data Memory from ACC  
1
SUB A,[m]  
SUBM A,[m]  
SBC A,[m]  
SBCM A,[m]  
DAA [m]  
1
1Note  
Subtract Data Memory from ACC with result in Data Memory  
Subtract Data Memory from ACC with Carry  
Subtract Data Memory from ACC with Carry, result in Data Memory  
Decimal adjust ACC for Addition with result in Data Memory  
1
1Note  
1Note  
Logic Operation  
AND A,[m]  
OR A,[m]  
XOR A,[m]  
ANDM A,[m]  
ORM A,[m]  
XORM A,[m]  
AND A,x  
Logical AND Data Memory to ACC  
Logical OR Data Memory to ACC  
Logical XOR Data Memory to ACC  
Logical AND ACC to Data Memory  
Logical OR ACC to Data Memory  
Logical XOR ACC to Data Memory  
Logical AND immediate Data to ACC  
Logical OR immediate Data to ACC  
Logical XOR immediate Data to ACC  
Complement Data Memory  
1
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note  
1Note  
1Note  
1
OR A,x  
1
XOR A,x  
1
1Note  
CPL [m]  
CPLA [m]  
Complement Data Memory with result in ACC  
1
Increment & Decrement  
INCA [m]  
INC [m]  
Increment Data Memory with result in ACC  
1
Z
Z
Z
Z
Increment Data Memory  
1Note  
DECA [m]  
DEC [m]  
Decrement Data Memory with result in ACC  
Decrement Data Memory  
1
1Note  
Rev. 2.01  
21  
January 9, 2009  
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