HT48R50A-1/HT48C50-1
The functional unit chip reset status are shown below.
Program Counter
Interrupt
Prescaler
WDT
Timer/Event Counter
Input/Output Ports
Stack Pointer
000H
Disable
Clear
Clear. After master reset, WDT begins counting
Off
Input mode
Points to the top of the stack
The states of the registers is summarized in the table.
Register
TMR0
TMR0C
TMR1H
TMR1L
TMR1C
Program
Counter
MP0
MP1
ACC
TBLP
TBLH
STATUS
INTC
WDTS
PA
PAC
PB
PBC
PC
PCC
PD
PDC
PG
PGC
Note:
Reset
(Power-on)
xxxx xxxx
00-0 1000
xxxx xxxx
xxxx xxxx
00-0 1---
000H
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx
--00 xxxx
-000 0000
0000 0111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
---- -111
---- -111
²*²
stands for
²warm
reset²
²u²
stands for
²unchanged²
²x²
stands for
²unknown²
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
xxxx xxxx
00-0 1000
xxxx xxxx
xxxx xxxx
00-0 1---
000H
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
--1u uuuu
-000 0000
0000 0111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
---- -111
---- -111
xxxx xxxx
00-0 1000
xxxx xxxx
xxxx xxxx
00-0 1---
000H
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
--uu uuuu
-000 0000
0000 0111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
---- -111
---- -111
RES Reset
(HALT)
xxxx xxxx
00-0 1000
xxxx xxxx
xxxx xxxx
00-0 1---
000H
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
--01 uuuu
-000 0000
0000 0111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
---- -111
---- -111
WDT Time-out
(HALT)*
uuuu uuuu
uu-u uuuu
uuuu uuuu
uuuu uuuu
uu-u u---
000H
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
--11 uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
---- -uuu
Rev. 2.01
13
January 9, 2009
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
