HT48R50A-1/HT48C50-1
There are 3 registers related to Timer/Event Counter 1;
TMR1H (0FH), TMR1L (10H), TMR1C (11H). Writing
TMR1L will only put the written data to an internal
lower-order byte buffer (8 bits) and writing TMR1H will
transfer the specified data and the contents of the
lower-order byte buffer to TMR1H and TMR1L preload
registers, respectively. The Timer/Event Counter 1
preload register is changed by each writing TMR1H op-
erations. Reading TMR1H will latch the contents of
TMR1H and TMR1L counters to the destination and the
lower-order byte buffer, respectively. Reading the
TMR1L will read the contents of the lower-order byte
buffer. The TMR1C is the Timer/Event Counter 1 control
register, which defines the operating mode, counting en-
able or disable and active edge.
In the pulse width measurement mode with the
T0ON/T1ON and T0E/T1E bits equal to one, once the
TMR0/TMR1 has received a transient from low to high
(or high to low if the T0E/T1E bits is ²0²) it will start
counting until the TMR0/TMR1 returns to the original
level and resets the T0ON/T1ON. The measured result
will remain in the Timer/Event Counter 0/1 even if the
activated transient occurs again. In other words, only
one cycle measurement can be done. Until setting the
T0ON/T1ON, the cycle measurement will function again
as long as it receives further transient pulse. Note that,
in this operating mode, the Timer/Event Counter 0/1
starts counting not according to the logic level but ac-
cording to the transient edges. In the case of counter
overflows, the counter 0/1 is reloaded from the
Timer/Event Counter 0/1 preload register and issues the
interrupt request just like the other two modes. To en-
able the counting operation, the timer ON bit (T0ON: bit
4 of TMR0C; T1ON: bit 4 of TMR1C) should be set to 1.
In the pulse width measurement mode, the T0ON/T1ON
will be cleared automatically after the measurement cy-
cle is completed. But in the other two modes the
T0ON/T1ON can only be reset by instructions. The
overflow of the Timer/Event Counter 0/1 is one of the
wake-up sources. No matter what the operation mode
is, writing a 0 to ET0I/ET1I can disable the correspond-
ing interrupt services.
The T0M0, T0M1 (TMR0C), T1M0, T1M1 (TMR1C) bits
define the operating mode. The event count mode is
used to count external events, which means the clock
source comes from an external (TMR0/TMR1) pin. The
timer mode functions as a normal timer with the clock
source coming from the fINT clock/instruction clock or RTC
clock (Timer0/Timer1). The pulse width measurement
mode can be used to count the high or low level duration of
the external signal (TMR0/TMR1). The counting is based
on the fINT clock/instruction clock or RTC clock
(Timer0/Timer1).
In the event count or timer mode, once the Timer/Event
Counter 0/1 starts counting, it will count from the current
contents in the Timer/Event Counter 0/1 to FFH or FFFFH.
Once overflow occurs, the counter is reloaded from the
Timer/Event Counter 0/1 preload register and generates
the interrupt request flag (T0F/T1F; bit 5/6 of INTC) at the
same time.
In the case of Timer/Event Counter 0/1 OFF condition,
writing data to the Timer/Event Counter 0/1 register
will also reload that data to the Timer/Event Counter 0/1.
But if the Timer/Event Counter 0/1 is turned on, data
written to it will only be kept in the Timer/Event Counter
0/1 preload register. The Timer/Event Counter 0/1 will still
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Timer/Event Counter 1
Rev. 2.01
15
January 9, 2009
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
