HT46R068B/HT46R069B
Enhanced A/D Type 8-bit OTP MCU
SPIA Serial Interface – SPIA
The devices contain an independent SPIA function, known as the SPIA. It is important not to
confuse this independent SPIA function with the additional one contained within the combined
SIM function, which is described in another section of this datasheet.
The device includes a single SPIA Serial Interface. The SPIA interface is a full duplex serial data
link, originally designed by Motorola, which allows multiple devices connected to the same SPIA
bus to communicate with each other. The devices communicate using a master/slave technique
where only the single master device can initiate a data transfer. A simple four line signal bus is
used for all communication and these pins are shared with normal I/O pins. The SPIA function is
selected via a configuration option.
SPIA Interface Communication
Four lines are used for SPIA communication known as SDIA - Serial Data Input, SDOA - Serial
Data Output, SCKA - Serial Clock and SCSA - Slave Select. Note that the condition of the
Slave Select line is conditioned by the CSEN bit in the SBCR control register. If the CSEN bit is
high then the SCSA line is active while if the bit is low then the SCSA line will be in a floating
condition. The following timing diagram depicts the basic timing protocol of the SPIA bus.
SPIA Registers
There are two registers associated with the SPIA Interface. These are the SBCR register which is
the control register and the SBDR which is the data register. The SBCR register is used to setup the
required setup parameters for the SPIA bus and also used to store associated operating flags, while
the SBDR register is used for data storage.
After Power on, the contents of the SBDR register will be in an unknown condition while the
SBCR register will default to the condition below:
CKS
M1
M0
SBEN
MLSA
CSENA
WCOLA
TRFA
0
1
1
0
0
0
0
0
Note that data written to the SBDR register will only be written to the TXRX buffer, whereas data
read from the SBDR register will actual be read from the register.
SPIA Bus Enable/Disable
To enable the SPIA bus, CSEN = 1, SCSA=0, then wait for data to be written to the SBDR
(TXRX bufffer) register. For the Master Mode, after data has been written to the SBDR (TXRX
buffer) register, then transmission or reception will start automatically. When all the data has been
transferred the TRF bit should be set. For the Slave Mode, when clock pulses are received on
SCKA, data in the TXRX buffer will be shifted out or data on SDIA will be shifted in.
To Disable the SPIA bus SCKA, SDIA, SDOA, SCSA should be in a floating condition.
Rev. 1.00
98
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HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
