HT46R64/HT46C64
V
D
D
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
m
0 . 0 1 F *
1
0
0
k
Reset
R
E
S
There are three ways in which reset may occur.
1
0
k
·
·
·
RES is reset during normal operation
RES is reset during HALT
m
0 . 1 F *
WDT time-out is reset during normal operation
The WDT time-out during HALT differs from other chip
reset conditions, for it can perform a ²warm reset² that
resets only the program counter and SP and leaves the
other circuits at their original state. Some registers re-
main unaffected during any other reset conditions. Most
registers are reset to the ²initial condition² once the re-
set conditions are met. Examining the PDF and TO
flags, the program can distinguish between different
²chip resets².
Reset Circuit
Note:
²*² Make the length of the wiring, which is con-
nected to the RES pin as short as possible, to
avoid noise interference.
V
D
D
R
E
S
t
S S T
TO PDF
RESET Conditions
RES reset during power-up
RES reset during normal operation
RES Wake-up HALT
S
S
T
T
i
m
e
-
o
u
t
0
u
0
1
1
0
u
1
u
1
C
h
i
p
R
e
s
e
t
Reset Timing Chart
WDT time-out during normal operation
WDT Wake-up HALT
H
A
L
T
W
a
r
m
R
e
s
e
t
W
D
T
Note: ²u² stands for unchanged
W
D
T
T
i
m
e
-
o
u
t
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem awakes from the HALT state or during power up.
Awaking from the HALT state or system power-up, the
SST delay is added.
R
e
s
e
t
E
x
t
e
r
n
a
l
R
E
S
C
o
l
d
S
S
T
R
e
s
e
t
1
0
-
b
i
t
R
i
p
p
l
e
O
S
C
1
C
o
u
n
t
e
r
P
o
w
e
r
-
o
n
D
e
t
e
c
t
i
o
n
An extra SST delay is added during the power-up pe-
riod, and any wake-up from HALT may enable only the
SST delay.
Reset Configuration
The functional unit chip reset status is shown below.
Program Counter
Interrupt
000H
Disabled
Cleared
Prescaler, Divider
Cleared. After master reset,
WDT starts counting
WDT, RTC, Time Base
Timer/event Counter
Input/output Ports
Stack Pointer
Off
Input mode
Points to the top of the stack
Rev. 1.80
15
February 14, 2006
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
