HT46R47-H
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is sub-
sequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 6 return ad-
dresses are stored).
The special function registers include the indirect ad-
dressing register (00H), timer/event counter
(TMR;0DH), timer/event counter control register
(TMRC;0EH), program counter lower-order byte regis-
ter (PCL;06H), memory pointer register (MP;01H), ac-
cumulator (ACC;05H), table pointer (TBLP;07H), table
higher-order byte register (TBLH;08H), status register
(STATUS;0AH), interrupt control register (INTC;0BH),
PWM data register (PWM;1AH), the A/D result
lower-order byte register (ADRL;20H), the A/D result
higher-order byte register (ADRH;21H), the A/D control
register (ADCR;22H), the A/D clock setting register
(ACSR;23H), I/O registers (PA;12H, PB;14H, PD;18H)
and I/O control registers (PAC;13H, PBC;15H,
PDC;19H). The remaining space before the 40H is re-
served for future expanded usage and reading these lo-
cations will get ²00H². The general purpose data
memory, addressed from 40H to 7FH, is used for data
and control information under instruction commands.
Data Memory - RAM
The data memory is designed with 85´8 bits. The data
memory is divided into two functional groups: special
function registers and general purpose data memory
(64´8). Most are read/write, but some are read only.
I
n
d
i
r
e
c
t
A
d
d
r
e
s
s
i
n
g
R
e
g
i
s
t
e
r
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
M
P
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer register (MP;01H).
A
C
C
P
C
L
T
B
L
P
T
B
L
H
S
T
A
T
U
S
0
0
A
B
H
H
Indirect Addressing Register
I
N
T
C
Location 00H is an indirect addressing register that is
not physically implemented. Any read/write operation of
[00H] accesses data memory pointed to by MP (01H).
Reading location 00H itself indirectly will return the re-
sult 00H. Writing indirectly results in no operation.
0
0
C
D
H
H
T
M
R
T
M
R
C
0
E
H
0
F
H
H
H
H
H
H
H
H
H
H
H
1
1
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
8
9
S
p
e
c
i
a
l
P
u
r
p
o
s
e
The memory pointer register MP (01H) is a 7-bit register.
The bit 7 of MP is undefined and reading will return the
result ²1². Any writing operation to MP will only transfer the
lower 7-bit data to MP.
D
a
t
a
M
e
m
o
r
y
P
P
A
B
P
P
A
B
C
C
Accumulator
P
D
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
P
D
C
1
1
A
B
H
H
P
W
M
1
1
C
D
H
H
1
E
H
Arithmetic and Logic Unit - ALU
1
F
H
2
2
2
0
1
2
H
H
H
A
D
R
L
This circuit performs 8-bit arithmetic and logic opera-
tions. The ALU provides the following functions:
A
A
D
D
R
C
H
R
·
·
·
·
·
Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
Logic operations (AND, OR, XOR, CPL)
Rotation (RL, RR, RLC, RRC)
2
3
H
A
C
S
R
2
3
4
F
H
H
4
0
H
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ ....)
G
e
n
e
r
a
l
P
u
r
p
o
s
e
:
U
n
u
s
e
d
D
a
t
a
M
e
m
o
r
y
(
6
4
B
y
t
e
s
)
R
e
a
d
a
s
"
0
0
"
The ALU not only saves the results of a data operation but
also changes the status register.
7
F
H
RAM Mapping
Rev. 1.30
9
March 1, 2006
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
