HT46R47-H
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Program Memory - ROM
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The program memory is used to store the program in-
structions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
2K´14 bits, addressed by the program counter and table
pointer.
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Certain locations in the program memory are reserved
for special usage:
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Location 000H
This area is reserved for program initialization. After
chip reset, the program always begins execution at lo-
cation 000H.
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Location 004H
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This area is reserved for the external interrupt service
program. If the INT input pin is activated, the interrupt
is enabled and the stack is not full, the program begins
execution at location 004H.
Program Memory
Service Routine) both employ the table read
instruction, the contents of the TBLH in the main
routine are likely to be changed by the table read
instruction used in the ISR. Errors can occur. In other
words, using the table read instruction in the main
routine and the ISR simultaneously should be
avoided. However, if the table read instruction has to
be applied in both the main routine and the ISR, the
interrupt is supposed to be disabled prior to the table
read instruction. It will not be enabled until the TBLH
has been backed up. All table related instructions
require two cycles to complete the operation. These
areas may function as normal program memory
depending upon the requirements.
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Location 008H
This area is reserved for the timer/event counter inter-
rupt service program. If a timer interrupt results from a
timer/event counter overflow, and if the interrupt is en-
abled and the stack is not full, the program begins exe-
cution at location 008H.
Location 00CH
This area is reserved for the A/D converter interrupt
service program. If an A/D converter interrupt results
from an end of A/D conversion, and if the interrupt is
enabled and the stack is not full, the program begins
execution at location 00CH.
Table location
Stack Register - STACK
Any location in the ROM space can be used as
look-up tables. The instructions ²TABRDC [m]² (the
current page, 1 page=256 words) and ²TABRDL [m]²
(the last page) transfer the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
other bits of the table word are transferred to the lower
portion of TBLH, and the remaining 2 bits are read as
²0². The Table Higher-order byte register (TBLH) is
read only. The table pointer (TBLP) is a read/write
register (07H), which indicates the table location.
Before accessing the table, the location must be
placed in TBLP. The TBLH is read only and cannot be
restored. If the main routine and the ISR (Interrupt
This is a special part of the memory which is used to
save the contents of the program counter only. The
stack is organized into 6 levels and are neither part of
the data nor part of the program space, and is neither
readable nor writeable. The activated level is indexed by
the stack pointer (SP) and is neither readable nor
writeable. At a subroutine call or interrupt acknowledg-
ment, the contents of the program counter are pushed
onto the stack. At the end of a subroutine or an interrupt
routine, signaled by a return instruction (RET or RETI),
the program counter is restored to its previous value
from the stack. After a chip reset, the SP will point to the
top of the stack.
Table Location
Instruction
*10
P10
1
*9
P9
1
*8
P8
1
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
TABRDL [m]
@7
@7
@6
@6
@5
@5
@4
@4
@3
@3
@2
@2
@1
@1
@0
@0
Table Location
P10~P8: Current program counter bits
Note: *10~*0: Table location bits
@7~@0: Table pointer bits
Rev. 1.30
8
March 1, 2006
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
