HT46R47-H
·
·
The contents of the on chip RAM and registers remain
unchanged.
Watchdog Timer - WDT
The clock source of WDT is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (sys-
tem clock divided by 4), decided by options. This timer is
designed to prevent a software malfunction or sequence
from jumping to an unknown location with unpredictable
results. The Watchdog Timer can be disabled by an op-
tion. If the Watchdog Timer is disabled, all the execu-
tions related to the WDT result in no operation.
WDT will be cleared and recounted again (if the WDT
clock is from the WDT oscillator).
·
·
All of the I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a ²warm reset². After the TO and PDF flags are
examined, the reason for chip reset can be determined.
The PDF flag is cleared by system power-up or execut-
ing the ²CLR WDT² instruction and is set when execut-
ing the ²HALT² instruction. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
the program counter and SP; the others keep their origi-
nal status.
Once the internal oscillator (RC oscillator with a period
of 65ms at 5V normally) is selected, it is divided by
32768~65536 to get the time-out period of approxi-
mately 2.1s~4.3s. This time-out period may vary with
temperatures, VDD and process variations. If the WDT
oscillator is disabled, the WDT clock may still come from
the instruction clock and operate in the same manner
except that in the HALT state the WDT may stop count-
ing and lose its protecting purpose. In this situation the
logic can only be restarted by external logic.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by the options. Awakening from an I/O port stim-
ulus, the program will resume execution of the next in-
struction. If it is awakening from an interrupt, two
sequences may happen. If the related interrupt is dis-
abled or the interrupt is enabled but the stack is full, the
program will resume execution at the next instruction. If
the interrupt is enabled and the stack is not full, the regu-
lar interrupt response takes place. If an interrupt request
flag is set to ²1² before entering the HALT mode, the
wake-up function of the related interrupt will be disabled.
Once a wake-up event occurs, it takes 1024 tSYS (sys-
tem clock period) to resume normal operation. In other
words, a dummy period will be inserted after wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
The WDT overflow under normal operation will initialize
²chip reset² and set the status bit ²TO². But in the HALT
mode, the overflow will initialize a ²warm reset², and
only the program counter and SP are reset to zero. To
clear the contents of WDT, three methods are adopted;
external reset (a low level to RES), software instruction
and a HALT instruction. The software instruction include
²CLR WDT² and the other set - ²CLR WDT1² and ²CLR
WDT2². Of these two types of instruction, only one can
be active depending on the options - ²CLR WDT times
selection option². If the ²CLR WDT² is selected (i.e. CLR
WDT times equal one), any execution of the ²CLR
WDT² instruction will clear the WDT. In the case that
²CLR WDT1² and ²CLR WDT2² are chosen (i.e. CLR
WDT times equal two), these two instructions must be
executed to clear the WDT; otherwise, the WDT may re-
set the chip as a result of time-out.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Power Down Operation - HALT
Reset
The HALT mode is initialized by the ²HALT² instruction
and results in the following...
There are three ways in which a reset can occur:
·
The system oscillator will be turned off but the WDT
oscillator keeps running (if the WDT oscillator is se-
lected).
·
·
·
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
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Watchdog Timer
Rev. 1.30
12
March 1, 2006
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
