HT46R47-H
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re -
set² that resets only the program counter and SP, leav-
ing the other circuits in their original state. Some regis-
ters remain unchanged during other reset conditions.
Most registers are reset to the ²initial condition² when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
²chip resets².
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Reset Timing Chart
V
D
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m
0 . 0 1 F *
TO PDF
RESET Conditions
RES reset during power-up
RES reset during normal operation
RES wake-up HALT
1
0
0
k
0
u
0
1
1
0
u
1
u
1
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1
0
k
m
0 . 1 F *
WDT time-out during normal operation
WDT wake-up HALT
Reset Circuit
Note: ²u² means ²unchanged²
Note:
²*² Make the length of the wiring, which is con-
nected to the RES pin as short as possible, to
avoid noise interference.
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
H
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When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able the SST delay.
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An extra option load time delay is added during system
reset (power-up, WDT time-out at normal mode or RES
reset).
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1
0
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O
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1
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The functional unit chip reset status are shown below.
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Program Counter
Interrupt
000H
Reset Configuration
Disable
Clear. After master reset,
WDT begins counting
WDT
Timer/Event Counter Off
Input/Output Ports
Stack Pointer
Input mode
Points to the top of the stack
Rev. 1.30
13
March 1, 2006
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
