欢迎访问ic37.com |
会员登录 免费注册
发布采购

HT46R232(48SSOP-A) 参数 Datasheet PDF下载

HT46R232(48SSOP-A)图片预览
型号: HT46R232(48SSOP-A)
PDF下载: 下载PDF文件 查看货源
内容描述: [Microcontroller, 8-Bit, UVPROM, 8MHz, CMOS, PDSO48,]
分类和应用: 可编程只读存储器微控制器光电二极管
文件页数/大小: 48 页 / 354 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
 浏览型号HT46R232(48SSOP-A)的Datasheet PDF文件第8页浏览型号HT46R232(48SSOP-A)的Datasheet PDF文件第9页浏览型号HT46R232(48SSOP-A)的Datasheet PDF文件第10页浏览型号HT46R232(48SSOP-A)的Datasheet PDF文件第11页浏览型号HT46R232(48SSOP-A)的Datasheet PDF文件第13页浏览型号HT46R232(48SSOP-A)的Datasheet PDF文件第14页浏览型号HT46R232(48SSOP-A)的Datasheet PDF文件第15页浏览型号HT46R232(48SSOP-A)的Datasheet PDF文件第16页  
HT46R232/HT46C232  
S
y
s
t
e
m
C
l
o
c
k
/
4
8
s
f / 2  
M
a
s
k
f
s
W
D
T
P
r
e
s
c
a
l
e
r
D
i
v
i
d
e
r
o
p
t
i
o
n
s
e
l
e
c
t
W
D
T
C
K
T
C
K
T
T
i
m
e
-
o
u
t
R
e
s
e
t
M
a
s
k
O
p
t
i
o
n
O
S
C
1
1
1
1
5
4
3
2
1
1
1
1
6
5
4
3
R
R
2
/
f
S
S
S
S
~
~
~
~
2
2
2
2
/
/
/
/
f
f
f
f
S
S
S
S
2
2
/
/
f
f
W
D
T
C
l
e
a
r
2
/
f
Watchdog Timer  
the interrupt is enabled and the stack is not full, the regu-  
lar interrupt response takes place. When an interrupt re-  
quest flag is set to ²1² before entering the HALT mode,  
the wake-up function of the related interrupt will be dis-  
abled. If wake-up event occurs, it takes 1024 fSYS (sys-  
tem clock period) to resume normal operation. In other  
words, a dummy period is inserted after wake-up. If the  
wake-up results from an interrupt acknowledgment, the  
actual interrupt subroutine execution is delayed by more  
than one cycle. However, if the wake-up results in the  
next instruction execution, this will be executed per-  
formed immediately after the dummy period is finished.  
CLRWDT times equal one), any execution of the CLR  
WDT instruction will clear the WDT. In case ²CLR  
WDT1² and ²CLR WDT2² are chosen (i.e. CLRWDT  
times equal two), these two instructions must be exe-  
cuted to clear the WDT; otherwise, the WDT may reset  
the chip because of time-out.  
If the WDT time-out period is selected fs/212 (option), the  
WDT time-out period ranges from fs/212~fs/213, since the  
²CLR WDT² or ²CLR WDT1² and ²CLR WDT2²  
instructions only clear the last two stages of the WDT.  
Power Down Operation - HALT  
To minimize power consumption, all the I/O pins should  
be carefully managed before entering the HALT status.  
The HALT mode is initialized by the ²HALT² instruction  
and results in the following...  
Reset  
·
The system oscillator turned off but the WDT oscillator  
keeps running (if the WDT oscillator or the real time  
clock is selected).  
There are three ways in which a reset may occur:  
·
·
·
RES reset during normal operation  
RES reset during HALT  
·
·
The contents of the on-chip RAM and registers remain  
unchanged  
WDT time-out reset during normal operation  
The WDT will be cleared and start recounting (if the  
WDT clock source is from the WDT oscillator or the  
real time clock)  
The WDT time-out during HALT differs from other chip  
reset conditions, for it can perform a ²warm reset² that  
resets only the program counter and SP, leaves the  
other circuits at their original state. Some registers re-  
main unaffected during any other reset conditions. Most  
registers are reset to the ²initial condition² when the re-  
set conditions are met. Examining the PDF and TO  
flags, the program can distinguish between different  
²chip resets².  
·
·
All of the I/O ports maintain their original status  
The PDF flag is set and the TO flag is cleared  
The system quits the HALT mode by an external reset,  
an interrupt, an external falling edge signal on port Aor a  
WDT overflow. An external reset causes a device initial-  
ization and the WDT overflow performs a ²warm reset².  
After examining the TO and PDF flags, the reason for  
chip reset can be determined. The PDF flag is cleared  
by system power-up or by executing the ²CLR WDT² in-  
struction and is set when executing the ²HALT² instruc-  
tion. On the other hand, the TO flag is set if the WDT  
time-out occurs, and causes a wake-up that only resets  
the program counter and SP; and leaves the others in  
their original status.  
V
D
D
V
D D  
m
0 . 0 1 F  
1
0
0
k
W
1
0
0
k
R
E
S
R
E
S
m
0 . 1 F  
1
0
k
B
a
s
i
c
H
i
-
n
o
i
s
e
The port A wake-up and interrupt methods can be con-  
sidered as a continuation of normal execution. Each bit  
in port A can be independently selected to wake up the  
device by the option. Awakening from an I/O port stimu-  
lus, the program will resume execution of the next in-  
struction. If it is awakening from an interrupt, two  
sequences may occur. If the related interrupt is disabled  
or the interrupt is enabled but the stack is full, the pro-  
gram will resume execution at the next instruction. But if  
R
e
s
e
t
R
e
s
e
t
m
0 . 1 F  
C
i
r
c
u
i
t
C
i
r
c
u
i
t
Reset Circuit  
Note: Most applications can use the Basic Reset Cir-  
cuit as shown, however for applications with  
extensive noise, it is recommended to use the  
Hi-noise Reset Circuit.  
Rev. 1.50  
12  
January 21, 2009