HT45R38
edge signal on port A or a WDT overflow. An external re-
set causes a device initialisation and the WDT overflow
performs a ²warm reset². After the TO and PDF flags
are examined, the reason for chip reset can be deter-
mined. The PDF flag is cleared by a system power-up or
executing the ²CLR WDT² instruction and is set when
executing the ²HALT² instruction. The TO flag is set if a
WDT time-out occurs, and causes a wake-up that only
resets the program counter and SP; the other registers
maintain their their original status.
that it can perform a ²warm reset² that resets only the
Program Counter and the SP, leaving the other circuits
in their original state. Some registers remain unchanged
during other reset conditions. Most registers are reset to
their ²initial condition² when the reset conditions are
met. By examining the PDF and TO flags, the program
can distinguish between the different device reset types.
TO PDF
RESET Conditions
RES reset during power-up
RES reset during normal operation
RES wake-up HALT
0
u
0
1
1
0
u
1
u
1
The port A and interrupt methods of wake-up can be
considered as a continuation of normal execution. Each
bit in port A can be independently selected by configura-
tion options to wake-up the device. When awakened
from an I/O port stimulus, the program will resume exe-
cution at the next instruction. If it is awakened due to an
interrupt, two sequences may happen. If the related in-
terrupt is disabled or the interrupt is enabled but the
stack is full, the program will resume execution at the
next instruction. If the interrupt is enabled and the stack
is not full, the regular interrupt response takes place. If
an interrupt request flag is set to ²1² before entering the
Power Down mode, the wake-up function of the related
interrupt will be disabled. Once a wake-up event occurs,
it takes 1024 tSYS (system clock periods) to resume nor-
mal operation. In other words, a dummy period will be in-
serted after wake-up. If the wake-up results from an
interrupt acknowledgment, the actual interrupt subrou-
tine execution will be delayed by one or more cycles. If
the wake-up results in the next instruction execution,
this will be executed immediately after the dummy pe-
riod is finished.
WDT time-out during normal operation
WDT wake-up HALT
Note: ²u² means ²unchanged²
To guarantee that the system oscillator is started and
stabilised, the SST or System Start-up Timer, provides
an extra-delay of 1024 system clock pulses when the
system is reset (power-up, WDT time-out or RES reset)
or when the system awakens from a Power Down state.
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able the SST delay.
An extra option load time delay is added during a system
reset (power-up, WDT time-out at normal mode or RES
reset).
The functional unit device reset status are shown below.
Program Counter
Interrupt
000H
Disable
Clear
Prescaler
To minimise power consumption, all the I/O pins should
be carefully managed before entering the Power Down
Mode.
Clear. After master reset,
WDT begins counting
WDT
Timer/Event Counter Off
Reset
Input/Output Ports
Stack Pointer
Input mode
Points to the top of the stack
There are three ways in which a reset can occur:
·
·
·
RES reset during normal operation
RES reset during HALT
V
D
D
R
E
S
WDT time-out reset during normal operation
t
S
S
T
A WDT time-out, when the device is in the Power Down
mode, is different from other device reset conditions, in
S
S
T
T
i
m
e
-
o
u
t
C
h
i
p
R
e
s
e
t
V
D
D
Reset Timing Chart
m
0 . 0 1 F *
H
A
L
T
W
a
r
m
R
e
s
e
t
1
0
0
k
W
D
T
R
E
S
1
0
k
R
E
S
C
o
l
d
m
0 . 1 F *
R
e
s
e
t
S
S
T
1
0
-
b
i
t
R
i
p
p
l
e
O
S
C
1
C
o
u
n
t
e
r
Reset Circuit
Note:
²*² Make the length of the wiring, which is con-
nected to the RES pin as short as possible, to
avoid noise interference.
S
y
s
t
e
m
R
e
s
e
t
Reset Configuration
Rev. 1.00
14
December 13, 2006
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
