HT45R38
A/D clock setting register (ACSR;2BH), the Operation
Amplifier control register (OPAC;26H), I/O registers
(PA;12H, PB;14H, PC;16H, PE;18H) and I/O control
registers (PAC;13H, PBC;15H, PCC;17H, PEC;19H).
The general purpose data memory, addressed from 40H
to FFH, is used for data and control information under in-
struction commands.
registers is not supported. The memory pointer regis-
ters, MP0 and MP1, are both 8-bit registers used to ac-
cess the Program Memory by combining corresponding
indirect addressing registers.
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location ²05H² of the data memory
and can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by the ²SET [m].i²
and ²CLR [m].i² bit manipulation instructions. They are
also indirectly accessible through the memory pointer
registers (MP0;01H, MP1;02H).
Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic opera-
tions. The ALU provides the following functions:
Indirect Addressing Register
·
·
·
·
·
Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
Logic operations (AND, OR, XOR, CPL)
Rotation (RL, RR, RLC, RRC)
The method of indirect addressing allows data manipu-
lation using memory pointers instead of the usual direct
memory addressing method where the actual memory
address is defined. Any action on the indirect address-
ing registers will result in corresponding read/write oper-
ations to the memory location specified by the
corresponding memory pointers. This device contains
two indirect addressing registers known as IAR0 and
IAR1 and two memory pointers MP0 and MP1. Note that
these indirect addressing registers are not physically
implemented and that reading the indirect addressing
registers indirectly will return a result of ²00H² and writ-
ing to the registers indirectly will result in no operation.
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
The two memory pointers, MP0 and MP1, are physically
implemented in the data memory and can be manipu-
lated in the same way as normal registers providing a
convenient way with which to address and track data.
When any operation to the relevant indirect addressing
registers is carried out, the actual address that the
microcontroller is directed to is the address specified by
the related memory pointer.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition opera-
tions related to the status register may give different re-
sults from those intended. The TO flag can be affected
only by a system power-up, a WDT time-out or execut-
ing the ²CLR WDT² or ²HALT² instruction.
Direct data transfer between two indirect addressing
Bit No.
Label
Function
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
0
C
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
1
2
3
AC
Z
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
OV
PDF is cleared by system power-up or executing the ²CLR WDT² instruction.
PDF is set by executing the ²HALT² instruction.
4
PDF
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
5
TO
6~7
¾
Unused bit, read as ²0²
Status (0AH) Register
Rev. 1.00
10
December 13, 2006
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
