HT45R38
The PDF flag can be affected only by executing a
²HALT² or ²CLR WDT² instruction or a system
power-up.
generated when the timer overflows. After the interrupt
is enabled, and the stack is not full, and the T0F bit is
set, a subroutine call to location ²0CH² will occur. The
related interrupt request flag, T0F, is reset, and the EMI
bit is cleared to disable other interrupts.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
The internal Timer/Event Counter 1 interrupt is initial-
ized by setting the Timer/Event Counter 1 interrupt re-
quest flag (T1F; bit 5 of INTC1), which is normally
caused by a timer overflow. After the interrupt is en-
abled, and the stack is not full, and the T1F bit is set, a
subroutine call to location ²14H² occurs. The related in-
terrupt request flag (T1F) is reset, and the EMI bit is
cleared to disable other interrupts.
In addition, on entering the interrupt sequence or exe-
cuting the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can cor-
rupt the status register, precautions must be taken to
save it properly.
Interrupt
The external RC Oscillation Converter interrupt is initial-
ized by setting the external RC Oscillation Converter in-
terrupt request flag, RCOCF; bit 4 of INTC1. This is
caused by a Timer A or Timer B overflow. When the inter-
rupt is enabled, and the stack is not full and the RCOCF
bit is set, a subroutine call to location ²10H² will occur.
The related interrupt request flag, RCOCF , will be reset
and the EMI bit cleared to disable further interrupts.
The devices provides two external interrupts, two inter-
nal 8-bit timer/event counter interrupt, one external RC
oscillation converter interrupt and the A/D converter in-
terrupt. The interrupt control register 0 (INTC0;0BH) and
interrupt control register 1 (INTC1;1EH) both contain the
interrupt control bits that are used to set the enable/dis-
able and interrupt request flags.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked, by clearing the EMI bit. This
scheme may prevent further interrupt nesting. Other in-
terrupt requests may happen during this interval but only
the interrupt request flag is recorded. If a certain inter-
rupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC0 and
INTC1 registers may be set to allow interrupt nesting. If
the stack is full, the interrupt request will not be acknowl-
edged, even if the related interrupt is enabled, until the
SP is decremented. If immediate service is desired, the
stack must be prevented from becoming full.
The A/D converter interrupt is initialised by setting the
A/D converter request flag (ADF; bit 6 of the INTC1),
caused by an end of A/D conversion. When the interrupt
is enabled, the stack is not full and the ADF is set, a sub-
routine call to location 18H will occur. The related inter-
rupt request flag (ADF) will be reset and the EMI bit
cleared to disable further interrupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are held until the ²RETI² in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1, if the stack is not full. To
return from the interrupt subroutine, a ²RET² or ²RETI²
instruction may be invoked. RETI will set the EMI bit to
enable an interrupt service, but RET will not.
All interrupts have a wake-up capability. As an interrupt
is serviced, a control transfer occurs by pushing the pro-
gram counter onto the stack, followed by a branch to a
subroutine at a specified location in the program mem-
ory. Only the program counter is pushed onto the stack.
If the contents of the accumulator or status register are
altered by the interrupt service program, this may cor-
rupt the desired control sequence, therefore their con-
tents should be saved in advance.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
External interrupts are triggered by an edge transition
on pins INT0 or INT1. A configuration option enables
these pins as interrupts and selects if they are active on
high to low or low to high transitions. If active their re-
lated interrupt request flag, EIF0; bit 4 in INTC0, and
EIF1; bit 5 in INTC0, will be set. After the interrupt is en-
abled, the stack is not full, and the external interrupt is
active, a subroutine call to location ²04H² or ²08H² will
occur. The interrupt request flags, EIF0 or EIF1, and the
EMI bit will all be cleared to disable other interrupts.
Interrupt Source
External Interrupt 0
Priority Vector
1
2
3
04H
08H
0CH
External Interrupt 1
Timer/Event Counter 0 Overflow
External RC Oscillation Converter
Interrupt
4
10H
Timer/Event Counter 1 Overflow
A/D Converter Interrupt
5
6
14H
18H
The internal Timer/Event Counter 0 interrupt is initial-
ised by setting the Timer/Event Counter 0 interrupt re-
quest flag,T0F; bit 6 in INTC0. A timer interrupt will be
Interrupt Priority
Rev. 1.00
11
December 13, 2006
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
