HT45R38
Timer/Event Counter 0/1
In the event count or timer mode, the timer/event coun-
ter 0/1 starts counting at the current contents in the
timer/event counter and ends at FFH. Once an overflow
occurs, the counter is reloaded from the timer/event
counter preload register, and generates an interrupt re-
quest flag, which is the T0F; bit 6 of INTC0, or the T1F;
bit 5 of INTC1.
Two timer/event counters are implemented in the
microcontroller. Timer/Event Counter 0 is an 8-bit pro-
grammable count-up counter whose clock may come
from an external source or from an internal clock source.
This internal clock source is the system clock.
Timer/Event Counter 1 is also an 8-bit programmable
count-up counter whose clock may come from an exter-
nal source or from an internal clock source. This internal
clock source is the system clock/4. Using an external
clock input allows the user to count external events,
measure time intervals or pulse widths. Using the inter-
nal clock allows an accurate time base to be generated.
In the pulse width measurement mode with the values of
the T0ON/T1ON and T0E/T1E bits equal to ²1², after the
TMR0 or TMR1 pin has received a low to high transient,
or high to low if the T0E/T1E bit is ²0², it will start count-
ing until the TMR0 or TMR1 pin returns to its original
level at which point it will reset the T0ON/T1ON bit.
There are two registers related to Timer/Event Counter
0; TMR0 (0DH), TMR0C (0EH), and two registers re-
lated to Timer/Event Counter 1; TMR1(10H), TMR1C
(11H). Writing to either Timer/Event Counter places a
start value in the Timer/Event Counter 0/1 preload regis-
ter while reading the Timer/Event Counter retrieves the
contents of the Timer/Event Counter 0/1. The TMR0C
and TMR1C registers are the Timer/Event Counter con-
trol register 0/1, which define the operating mode, the
count enable or disable and the active edge type.
The measured result remains in the timer/event counter
even if the activated transient occurs again. In other
words, only a single shot measurement can be made.
Not until the T0ON/T1ON bit is set again, by the pro-
gram, can another measurement be made. In this oper-
ation mode, the timer/event counter begins counting not
according to the logic level but according to the transient
edges. In the case of counter overflows, the counter is
reloaded from the timer/event counter register and is-
sues an interrupt request, as in the other two modes,
i.e., event counter and timer modes.
The T0M0/T1M0 and T0M1/T1M1 bits define the opera-
tion mode. The event count mode is used to count exter-
nal events, which means that the clock source will come
from the external timer pin, TMR0 or TMR1. The timer
mode functions as a normal timer with the clock source
coming from the internal system clock. The pulse width
measurement mode can be used to measure the dura-
tion of a high or low level external signal on pin TMR0 or
TMR1. The counting will be based on the internally se-
lected clock source.
To enable the counting operation, the Timer ON bit,
T0ON; bit 4 of the TMR0C register or T1ON; bit 4 of the
TMR1C register, should be set to 1. In the pulse width
measurement mode, the T0ON/T1ON bit is automati-
cally cleared after the measurement cycle is completed.
But in the other two modes, the T0ON/T1ON bit can only
be reset by instructions. The overflow of the
Timer/Event Counter 0/1 is one of the wake-up sources.
No matter what the operation mode is, writing a 0 to
ET0I or ET1I disables the related interrupt servicing.
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Timer/Event Counter 1
Rev. 1.00
16
December 13, 2006
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
