ꢃꢅ-bit �RM Coꢁtex™-Mꢃ MCU
HTꢃꢅF1ꢅ51/51B/5ꢅ/5ꢃ
Table 2. HT32F125x Pin Descriptions
Pins
Description
AF1
IO
Pin
Name
Type
Level
48
LQFP
Default function
(AF0)
(Note1)
AF2
AF3
(Note2)
VSS�_ꢅ
P�0
P�1
P�ꢅ
P�ꢃ
P�4
P�5
P�6
P�7
P�8
P�9
P�10
1
ꢅ
ꢃ
4
5
6
7
8
9
P
Gꢁound ꢁefeꢁence foꢁ �DC and OP�/Comꢀaꢁatoꢁ
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO P�0
�DC_IN0
�DC_IN1
�DC_INꢅ
�DC_INꢃ
�DC_IN4
�DC_IN5
�DC_IN6
�DC_IN7
GT1_ETI
GT0_CHꢃ
GT0_CHꢅ
GT0_CH1
GT0_CH0
SPI_MOSI
SPI_MISO
GPIO P�1
GPIO P�ꢅ
UR_DCD
UR_DSR
UR_DTR
UR_RI
GPIO P�ꢃ
GPIO P�4
GPIO P�5
GPIO P�6
UR_RTS/TXE SPI_SCK
UR_CTS/SCK SPI_SEL
UR_RX
GPIO P�7
10
11
1ꢅ
5V-T
GPIO P�8
5V-T
5V-T
GPIO P�9-BOOT0
GPIO P�10-BOOT1
UR_TX
LDO 1.8 V output. Please put a 10μF capacitor to GND in those pins
as cꢂose as ꢀossibꢂe.
VLDOOUT 1ꢃ
P
N.C
14
15
16
LDO ꢃ.ꢃ V ꢀoweꢁ souꢁceꢄ aꢂso connected to the ꢀoweꢁ switch of the
backuꢀ domain.
VLDOIN
VSSLDO
P
P
I
LDO gꢁound ꢁefeꢁence
nRST
17
18
(Backuꢀ 5V-T
domain)
Exteꢁnaꢂ ꢁeset ꢀin and exteꢁnaꢂ wakeuꢀ ꢀin in Poweꢁ-Down mode
VDD ꢃ.ꢃ V foꢁ backuꢀ domain
(noteꢃ)
VB�T
P
I/O
(Backuꢀ
domain)
PB8(noteꢃ) 19
PB9(noteꢃ) ꢅ0
XT�LꢃꢅKIN
XT�LꢃꢅKOUT
RTCOUT
PB8
PB9
I/O
(Backuꢀ
domain)
I/O
PB10-
W�KEUP
PB10
ꢅ1
(Backuꢀ 5V-T
domain)
GT0_ETI
PB11
P�11
P�1ꢅ
P�1ꢃ
P�14
P�15
VDDꢃꢃ_ꢅ
VSSꢃꢃ_ꢅ
VSSꢃꢃ_ꢃ
PB1ꢅ
ꢅꢅ
ꢅꢃ
ꢅ4
ꢅ5
ꢅ6
ꢅ7
ꢅ8
ꢅ9
ꢃ0
ꢃ1
I/O
I/O
I/O
I/O
I/O
I/O
P
5V-T
5V-T
5V-T
5V-T
5V-T
5V-T
GPIO PB11
GPIO P�11
GPIO P�1ꢅ
SWDIO
CKOUT
IꢅC_SCL
IꢅC_SD�
P�1ꢃ
GT0_CHꢃ
GT0_CHꢅ
GT0_CH1
GT0_CH0
SWCLK
P�14
TR�CESWO
P�15
ꢃ.ꢃ V voꢂtage foꢁ digitaꢂ I/O
P
Gꢁound ꢁefeꢁence foꢁ digitaꢂ I/O
Gꢁound ꢁefeꢁence foꢁ digitaꢂ coꢁe
P
I/O
5V-T
GPIO PB1ꢅ
SPI_SEL
UR_DCD
GT1_CHꢃ
Rev. 1.10
ꢅ0 of ꢃ5
�ꢀꢁiꢂ 1ꢃꢄ ꢅ01ꢅ
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
