ꢃꢅ-bit �RM Coꢁtex™-Mꢃ MCU
HTꢃꢅF1ꢅ51/51B/5ꢅ/5ꢃ
Clock Structure
Pꢁescaꢂeꢁ
÷1ꢄ ꢅ
CK_US�RT
8 MHz
PLLSRC
PLLEN
PLL
HSI RC
UREN
f CK_PLL,max = 144MHz
1
0
CK_PLL
HSIEN
STCLK
(to SysTick)
÷8
SW[1:0]
4-16 MHz
HSE XT�L
fCK_SYS,max = 144MHz
fCK_AHB,max = 72MHz
0x
11
10
�HB
CK_SYS
CK_�HB
CK_HSI
CK_HSE
FCLK
( fꢁee ꢁunning cꢂock)
Pꢁescaꢂeꢁ
÷ 1ꢄꢅꢄ4ꢄ8
HSEEN
HCLKC
Cꢂock
( to Coꢁtex-Mꢃ)
Monitoꢁ
CMꢃEN
(contꢁoꢂ by HW)
CK_LSE
ꢃꢅ.768 kHz
LSE OSC
WDTSRC
HCLKF
( to Fꢂash)
LSEEN
1
0
CK_WDT
CMꢃEN
FMCEN
ꢃꢅ kHz
LSI RC
CK_LSI
WDTEN
HCLKS
RTCSRC
( to SR�M)
CMꢃEN
LSIEN
PCLK
SR�MEN
( to OP�ꢄ
�FIO
1
0
CK_RTC
GPIO Poꢁtꢄ
�DCꢄ
SPIꢄ
US�RTꢄ
IꢅCꢄ
GPTIMꢄ
EXTIꢄ
14
CKOUTSRC[ꢅ:0]
OP�0EN
14
WDTEN
(�PB ꢀeꢁiꢀheꢁaꢂs cꢂock gating)
RTCEN
000
001
010
CK_PLL/16
CK_�HB/16
CK_SYS/16
RTCꢄ
WDT)
CKOUT
011
100
101
110
CK_HSE/16
CK_HSI/16
CK_LSE
�DC
Pꢁescaꢂeꢁ
÷ 1ꢄꢅꢄ4ꢄ6ꢄ8...
CK_�DC
CK_LSI
�DCEN
Legend: HSE = High Sꢀeed Exteꢁnaꢂ cꢂock
HSI = High Sꢀeed Inteꢁnaꢂ cꢂock
LSE = Low Sꢀeed Exteꢁnaꢂ cꢂock
LSI = Low Sꢀeed Inteꢁnaꢂ cꢂock
NOTES: 1. Contꢁoꢂ bits LSIEN & LSEEN aꢁe ꢂocated at RTC Contꢁoꢂ Registeꢁ (RTCCR).
2. HTꢃꢅF1ꢅ51B does not incꢂude the VB�Tꢄ XT�LꢃꢅKIN and XT�LꢃꢅKOUT ꢀins.
Figure 3. HT32F125x Clock Structure Diagram
Rev. 1.10
17 of ꢃ5
�ꢀꢁiꢂ 1ꢃꢄ ꢅ01ꢅ
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
