ꢃꢅ-bit �RM Coꢁtex™-Mꢃ MCU
HTꢃꢅF1ꢅ51/51B/5ꢅ/5ꢃ
Memory Map
0xFFFF_FFFF
Reseꢁved
0xE010_0000
�HB Peꢁiꢀheꢁaꢂs
0x4010_0000
Pꢁivate ꢀeꢁiꢀheꢁaꢂ bus
Reseꢁved
0xE000_0000
0x4400_0000
Reseꢁved
CKCU/RSTCU
Reseꢁved
FMC
0x4008_�000
0x4008_8000
0x4008_ꢅ000
�PB/�HB bit band aꢂias
ꢃꢅ MB
0x4008_0000
0x4007_0000
0x4006_F000
0x4006_E000
0x4006_B000
0x4006_�000
0x4006_9000
0x4006_8000
0x4004_9000
0x4004_8000
0x400ꢅ_5000
0x400ꢅ_4000
0x400ꢅ_ꢃ000
0x400ꢅ_ꢅ000
0x4001_C000
0x4001_B000
0x4001_�000
0x4001_9000
0x4001_8000
0x4001_1000
0x4001_0000
0x4000_5000
0x4000_4000
0x4000_1000
0x4000_0000
0x4ꢅ00_0000
0x4010_0000
0x4008_0000
0x4000_0000
Reseꢁved
GPTM1
GPTM0
Reseꢁved
RTC/PWRCU
Reseꢁved
WDT
Peꢁiꢀheꢁaꢂs
Reseꢁved
51ꢅ KB
51ꢅ KB
�HB ꢀeꢁiꢀheꢁaꢂs
�PB ꢀeꢁiꢀheꢁaꢂs
Reseꢁved
0xꢅꢅ04_0000
0xꢅꢅ00_0000
0xꢅ000_ꢅ000
0xꢅ000_1000
0xꢅ000_0800
0xꢅ000_0000
0x1FF0_0400
0x1FF0_0000
0x1F00_0800
0x1F00_0000
Reseꢁved
IꢅC
SR�M bit band aꢂias
Reseꢁved
ꢅ56 KB
SR�M
Reseꢁved
EXTI
4 KB on-chiꢀ SR�M
ꢅ KB on-chiꢀ SR�M
ꢅ KB on-chiꢀ SR�M
Reseꢁved
HTꢃꢅF1ꢅ5ꢃ
Reseꢁved
�FIO
HTꢃꢅF1ꢅ5ꢅ
HTꢃꢅF1ꢅ51(B)
Reseꢁved
GPIO B
GPIO �
Reseꢁved
OP�/CMP
Reseꢁved
�DC
Oꢀtion Bytes Fꢂash
Reseꢁved
1 KB
ꢅ KB
Boot Loadeꢁ
Code
Reseꢁved
Reseꢁved
SPI
0x0000_7C00
0x0000_4000
0x0000_ꢅ000
0x0000_0000
15 KB on-chiꢀ Fꢂash
8 KB on-chiꢀ Fꢂash
8 KB on-chiꢀ Fꢂash
HTꢃꢅF1ꢅ5ꢃ
HTꢃꢅF1ꢅ5ꢅ
HTꢃꢅF1ꢅ51(B)
Reseꢁved
US�RT
�PB Peꢁiꢀheꢁaꢂs
NOTES: 1. Foꢁ HTꢃꢅF1ꢅ51(B)ꢄ the Fꢂash memoꢁy sꢀace at 0x0000_ꢅ000 to 0x0000_7BFF and the SR�M
memoꢁy sꢀace at 0xꢅ000_0800 to 0xꢅ000_1FFF aꢁe ꢁeseꢁved.
2. Foꢁ HTꢃꢅF1ꢅ5ꢅꢄ the Fꢂash memoꢁy sꢀace at 0x0000_4000 to 0x0000_7BFF and the SR�M memoꢁy
sꢀace at 0xꢅ000_1000 to 0xꢅ000_1FFF aꢁe ꢁeseꢁved.
Figure 2. HT32F125x Memory Map
Rev. 1.10
16 of ꢃ5
�ꢀꢁiꢂ 1ꢃꢄ ꢅ01ꢅ
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
