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Interrupt Control Registers
Interrupt Priority
External Interrupt
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In case of simultaneous requests,
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
For an external interrupt to occur, the global interrupt en-
able bit, EMI, and external interrupt enable bit, EEI, must
first be set. An actual external interrupt will take place
when the external interrupt request flag, EIF, is set, a situ-
ation that will occur when a high to low transition appears
on the INT line. The external interrupt pin is pin-shared
with the I/O pin PA5 and can only be configured as an ex-
ternal interrupt pin if the corresponding external interrupt
enable bit in the INTC 0 register has been set. The pin
must also be setup as an input by setting the correspond-
ing PAC.5 bit in the port control register. When the inter-
rupt is enabled, the stack is not full and a high to low
transition appears on the external interrupt pin, a subrou-
tine call to the external interrupt vector at location 04H,
will take place. When the interrupt is serviced, the exter-
nal interrupt request flag, EIF; bit 4 of INTC0 will be auto-
matically reset and the EMI bit will be automatically
cleared to disable other interrupts. Note that any pull-high
resistor configuration options on this pin will remain valid
even if the pin is used as an external interrupt input.
Interrupt Source
External Interrupt
All Devices Priority
1
2
3
4
Timer/Event Counter 0 Overflow
Timer/Event Counter 1 Overflow
A/D Converter Interrupt
In cases where both external and internal interrupts are
enabled and where an external and internal interrupt oc-
curs simultaneously, the external interrupt will always
have priority and will therefore be serviced first. Suitable
masking of the individual interrupts using the
INTC0/INTC1 register can prevent simultaneous occur-
rences.
Rev. 1.00
31
November 28, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
