14.2
Register Descriptions
14.2.1 System Control Register (SYSCR)
Bit
7
SSBY
0
6
STS2
0
5
STS1
0
4
STS0
0
3
XRST
1
2
NMIEG
0
1
HIE
0
0
RAME
1
Initial value
Read/Write
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
SYSCR is an 8-bit read/write register which controls chip operations. Host interface functions are
enabled or disabled by the HIE bit of SYSCR. See section 3.2, System Control Register, for
information on other SYSCR bits. SYSCR is initialized to H'09 by an external reset and in
hardware standby mode.
Bit 1—Host Interface Enable (HIE): Enables or disables the host interface. When enabled, the
host interface handles host-slave data transfers, operating in slave mode.
Bit 1: HIE
Description
0
1
The host interface is disabled
The host interface is enabled (slave mode)
(Initial value)
14.2.2 Host Interface Control Register (HICR)
Bit
7
6
5
4
3
2
1
0
—
1
—
1
—
1
—
1
—
1
IBFIE2 IBFIE1 FGA20E
Initial value
0
0
0
Slave Read/Write
Host Read/Write
—
—
—
—
—
—
—
—
—
—
R/W
—
R/W
—
R/W
—
HICR is an 8-bit read/write register which controls host interface interrupts and the fast A20 gate
function. HICR is initialized to H'F8 by a reset and in hardware standby mode.
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1.
321
HITACHI [ HITACHI SEMICONDUCTOR ]
