14.2.7 Output Data Register 2 (ODR2)
Bit
7
6
5
4
3
2
1
0
ODR7
—
ODR6
—
ODR5
—
ODR4
—
ODR3
—
ODR2
—
ODR1
—
ODR0
—
Initial value
Slave Read/Write
Host ead/WrRite
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RRRRRRRR
ODR2 is an 8-bit read/write register to the slave processor, and an 8-bit read-only register to the
host processor. The ODR2 contents are output on the host data bus when HA0 is low, CS2 is low,
and IOR is low.
The initial values of ODR2 after a reset or standby are undetermined.
14.2.8 Status Register 2 (STR2)
Bit
7
6
5
4
3
C/D
0
2
1
IBF
0
0
OBF
0
DBU
0
DBU
0
DBU
0
DBU
0
DBU
0
Initial value
Slave Read/Write
Host ead/WrRite
R/W
R/W
R/W
R/W
R
R/W
R
R
RRRRRRRR
STR2 is an 8-bit register that indicates status information during host interface processing. Bits 3,
1, and 0 are read-only bits to both the host and slave processors.
STR2 is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 4 and Bit 2—Defined by User (DBU): The user can use these bits as necessary.
Bit 3—Command/Data (C/D): Receives the HA0 input when the host processor writes to IDR2,
and indicates whether IDR2 contains data or a command.
Bit 3: C/D
Description
0
1
Contents of IDR2 are data
Contents of IDR2 are a command
(Initial value)
325
HITACHI [ HITACHI SEMICONDUCTOR ]
