Section 14 Host Interface
14.1
Overview
The H8/3437 Series has an on-chip host interface (HIF) that provides a dual-channel parallel
interface between the on-chip CPU and a host processor. The host interface is available only when
the HIE bit is set to 1 in SYSCR. This mode is called slave mode, because it is designed for a
master-slave communication system in which the H8/3437-Series chip is slaved to a host
processor.
The host interface consists of four 1-byte data registers, two 1-byte status registers, a 1-byte
control register, fast A20 gate logic, and a host interrupt request circuit. Communication is carried
out via five control signals from the host processor (CS1, CS2 or ECS2, HA0, IOR, andIOW or
EIOW), four output signals to the host processor (GA20, HIRQ1, HIRQ11, and HIRQ12), and an 8-
bit bidirectional command/data bus (HDB7 to HDB0, or XDB7 to XDB0). The CS1 and CS2 (or
ECS2) signals select one of the two interface channels.
Note: If one of the two interface channels will not be used, tie the unused CS pin to VCC. For
example, if interface channel 1 (IDR1, ODR1, STR1) is not used, tie CS1 to VCC.
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HITACHI [ HITACHI SEMICONDUCTOR ]
