•
Countermeasure
Figure 13.19 shows the recommended program flow.
Read IRIC in ICSR
IRIC = 1?
No
Yes
Write data to ICDR
Yes
Read ACKB in ICSR
No
Transmit
data present?
ACKB = 1?
Yes
No
Read SCL
No
SCL = 0?
Yes
Write 0 to BBSY and
0 to SCP in ICSR
Figure 13.19 Recommended Program Flow
•
•
Additional Note
When switching from master receive mode to master transmit mode, ensure that TRS is set to 1
before the last receive data is latched by reading ICDR.
Precautions when Clearing the IRIC Flag when Using the Wait Function
If the SCL rise time exceeds the specified duration when using the wait function in the I2C bus
interface’s master mode, or if there is a slave device that keeps SCL low and applies a wait
state, read SCL and clear the IRIC flag only after determining that SCL has gone low, as
shown below.
If the IRIC flag is cleared to 0 when WAIT is set to 1 and while the SCL high level duration is
being extended, the SDA value may change before SCL falls, erroneously resulting in a start or
stop condition.
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HITACHI [ HITACHI SEMICONDUCTOR ]
