•
Note on Issuance of Stop Condition
If the rise of SCL is weakened by external pull-up resistance R and bus load capacitance C in
master mode, or if SCL is pulled to the low level by a slave device, the timing at which SCL is
lowered by the internal bit synchronization circuit may be delayed by 1t SCL. If, in this case,
SCL is identified as being low at the bit synchronization circuit sampling timing, and a stop
condition issuing instruction is executed before the reference SCL clock next falls, as in figure
13.18, SDA will change from high to low to high while SCL remains high. As a result, a stop
condition will be issued before the end of the 9th clock.
Bit synchronization circuit sampling timing
Reference clock
High interval secured
9th clock not ended
SCL output
SDA output
Stop condition
9
9
Normal
operation
SCL output
SDA output
SCL
Stop condition
Erroneous
operation
VIH
SCL identified as low
Bus line
VIH
SDA
IRIC
Stop condition issuing instruction
execution timing
Normal operation
Erroneous
operation
Figure 13.18 Stop Condition Erroneous Operation Timing
313
HITACHI [ HITACHI SEMICONDUCTOR ]
