Bit 7—Input Edge Select A (IEDGA): This bit selects the rising or falling edge of the input
capture A signal (FTIA).
Bit 7: IEDGA
Description
0
1
Input capture A events are recognized on the falling edge of FTIA. (Initial value)
Input capture A events are recognized on the rising edge of FTIA.
Bit 6—Input Edge Select B (IEDGB): This bit selects the rising or falling edge of the input
capture B signal (FTIB).
Bit 6: IEDGB
Description
0
1
Input capture B events are recognized on the falling edge of FTIB. (Initial value)
Input capture B events are recognized on the rising edge of FTIB.
Bit 5—Input Edge Select C (IEDGC): This bit selects the rising or falling edge of the input
capture C signal (FTIC).
Bit 5: IEDGC
Description
0
1
Input capture C events are recognized on the falling edge of FTIC. (Initial value)
Input capture C events are recognized on the rising edge of FTIC.
Bit 4—Input Edge Select D (IEDGD): This bit selects the rising or falling edge of the input
capture D signal (FTID).
Bit 4: IEDGD
Description
0
1
Input capture D events are recognized on the falling edge of FTID. (Initial value)
Input capture D events are recognized on the rising edge of FTID.
Bit 3—Buffer Enable A (BUFEA): This bit selects whether to use ICRC as a buffer register for
ICRA.
Bit 3: BUFEA
Description
0
1
ICRC is used for input capture C.
ICRC is used as a buffer register for input capture A.
(Initial value)
167
HITACHI [ HITACHI SEMICONDUCTOR ]
